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| data sheet 28236-DSH-001-B may 2003 cn8236 atm servicesar plus with xbr traffic management the cn8236 service segmentation and reassembly controller integrates atm terminal functions, pci bus master and slave controllers, and a utopia level 1 or 2 interface with service-specific functions in a single package for aal0, 3/4, and 5 operations. the service sar controller generates and terminates atm traffic and automatically schedules cells for transmission. the cn8236 is targeted at 155 mbps throughput systems where the number of vccs is relatively large, or the performance of the overall system is critical. examples of such networking equipment include routers, ethernet switches, atm edge switches, or frame relay switches. service-specific performance accelerators the cn8236 incorporates numerous service-specific features designed to accelerate and enhance system performance. as examples, the cn8236 implements echo suppression of lan traffic via lecid filtering, and supports frame relay de to clp interworking. advanced xbr traffic management the xbr traffic manager in the cn8236 supports multiple atm service categories. this includes cbr, vbr (both single and dual leaky bucket), ubr, gfr (guaranteed frame rate), and abr. the cn8236 manages each vcc independently. it dynamically schedules segmentation traffic to comply with up to 16+cbr user-configured scheduling priorities for the various traffic classes. scheduling is controlled by a schedule table configured by the user and based on a user-specified time reference. abr channels are managed in hardware according to user-programmable abr templates. these templates tune the performance of the cn8236?s abr algorithms to a specific system?s or network?s requirements. ?continued? functional block diagram multi-client pci bus timer counters local bus pci master/ slave dma co- proc'r local memory interface segmentation coprocessor reassembly coprocessor cbr, vbr, abr, ubr, gfr traffic manager patent pending rx/tx utopia master/slave control/ status cn8236 cn8250 phy device cell fifo distinguishing features service-specific performance accelerators lecid filtering and echo suppression dual leaky bucket based on clp (frame relay) frame relay de interworking internal snmp mib counters ip over atm; supports both clp0+1 and abr shaping flexible architectures multi-peer host direct switch attachment via reverse utopia atm terminal ? host control ? local bus control optional local processor ? continued ?
? 1999-2003, mindspeed technologies?, a conexant business all rights reserved. information in this document is provided in connection with mindspeed technologies (?mindspeed?) products. these materials are provided by mindspeed as a service to its customers and may be used for informational purposes only. mindspeed assumes no responsibility for errors or omissions in these materials. mindspeed may make changes to specifications and product description s at any time, without notice. mindspeed makes no commitment to update the information and shall have no responsibility whatsoever f or conflicts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. exce pt as provided in mindspeed?s terms and conditions of sale for such products, mindspeed assumes no liability whatsoever. these materials are provided ?as is? without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including liability or warranties relating to fitness for a particular purpose, consequential or incidental damages, merchantability, or infringement of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. mindspeed customers using o r selling mindspeed products for use in such applications do so at their own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale. the following are trademarks of conexant systems, inc.: mindspeed technologies?, the mindspeed? logo, and ?build it first??. product names or services listed in this publication are for identification purposes only, and may be trademarks of third parti es. third-party brands and names are the property of their respective owners. for additional disclaimer information, please consult mindspeed technologies legal information posted at www.mindspeed.com which is incorporated by reference. 28236-DSH-001-B mindspeed technologies ? ordering information document revision history model number manufacturing part number product revision package operating temperature cn8236 28236-12 b 388-pin bga ? 40 c to 85 c cn8236/ cx28250evm evaluation module bt00-d700-601 ??? document number device revision comments n8236dsa cn8236 rev. a this is the advanced issue of the data sheet. 100453b cn8236 rev. b put into new conexant format. 500372a cn8236 rev. b revisions made. changed format from conexant to mindspeed. 500372b cn8236 rev. b corrections as noted by change bars. 28236-dsh-001-a cn8236 rev. b corrections as noted by change bars. 28236-DSH-001-B cn8236 rev. b corrections as noted by change bars. 28236-DSH-001-B mindspeed technologies ? ? continued from front ? multi-queue segmentation processing the cn8236 ? s segmentation coprocessor generates atm cells for up to 64 k vccs. the segmentation coprocessor formats cells on each channel according to segmentation vcc tables, utilizing up to 32 independent transmit queues and reporting segmentation status on a parallel set of up to 32 segmentation status queues. the segmentation coprocessor fetches client data from the host, formats atm cells while generating and appending protocol overhead, and forwards these to the utopia port. the segmentation coprocessor operates as a slave to the xbr traffic manager which schedules vccs for transmission. multi-queue reassembly processing the cn8236 ? s reassembly coprocessor stores the payload data from the cell stream received by the utopia port into host data buffers. using a dynamic lookup method which supports nni or uni addressing, the reassembly coprocessor processes up to 64 k vccs simultaneously. the host supplies free buffers on up to 32 independent free buffer queues, and the reassembly coprocessor performs all cpcs protocol checks and reports the results of these checks as well as other status data on one of 32 independent reassembly status queues. high performance host architecture with buffer isolation the cn8236 host interface architecture maximizes performance and system flexibility. the device ? s control and status queues enable host/sar communication via write operations alone. this write-only architecture lowers latency and pci bus occupancy. flexibility is achieved by supporting a scalable peer-to-peer architecture. multiple host clients can be addressed by the segmentation and reassembly (sar) as separate physical or logical pci peers. segmentation and reassembly data buffers on the host system are identified by buffer descriptors in sar-shared (or host) memory which contain pointers to buffers. the use of buffer descriptors in this way allows for isolation of data buffers from the mechanisms that handle buffer allocation and linking. this provides a layer of indirection in buffer assignment and management that maximizes system architecture flexibility. designer toolkit mindspeed provides an evaluation environment for the cn8236/rs8254evm which provides a working reference design, an example of a software driver, and facilities for generating and terminating all service categories of atm traffic. this system accelerates atm system development by providing a rapid prototyping environment. 28236-DSH-001-B mindspeed technologies ? ? continued distinguishing features ? new features 3.3 v, 388 bga lowers power and eases pcb assembly aal3/4 cpcs generation and checking pci 2.1, including support for serial eeprom enhancements to xbr traffic manager ? fewer abr templates ? improved cbr tunneling reduced memory size for vcc lookup tables increased addressing flexibility additional byte lane swappers for increased system flexibility utopia level 2, 8/16 bit 50 mhz programmable size routing tags up to 64 byte cells selectable single/separate utopia clocks interworking function for aal1 and 2 scheduling ? cell on demand scheduling updated pm-oam processing per i.610 secbc calculated per gr-1248 paging function in order to gluelessly control rs8228 cell delineator (sar provides power) robust eeprom operation compact pci hot swap capabilities master pci write over read arbitration control increase incoming dma fifo buffer from 2 kb to 8 kb prepended vcc index on rsm bom cells optional reference clock drive scheduler head of line flushing (holf) mechanism internal loopback in multiphy mode programmable number of slots that the scheduler can fall behind xbr traffic management tm4.1 service classes ? cbr ? vbr (single, dual and clp-based leaky buckets) ? real time vbr ? abr ? ubr ? gfc (controlled & uncontrolled flows) ? guaranteed frame rate (gfr) (guaranteed mcr on ubr vccs) 16 levels of priorities (16 + cbr) dynamic per-vcc scheduling multiple programmable abr templates (supplied by mindspeed or user) scheduler driven by selectable clock ? local system clock ? external reference clock internal rm oam cell feedback path virtual fifo buffer rate matching (source rate matching) per-vcc mcr and icr tunneling ? vp tunnels (vci interleaving on pdu boundaries) ? cbr tunnels (cells interleaved as ubr, vbr or abr with an aggregate cbr limit) 155 mbps full duplex (two cell pdus) multi-queue segmentation processing 32 transmit queues with optional priority levels 64 k vccs maximum aal5 and aal3/4 cpcs generation aal0 null cpcs (optional use of pti for pdu demarcation) atm cell header generation raw cell mode (52 octet) 200 mbps half duplex 155 mbps full duplex (w/ 2-cell pdus) variable length transmit fifo buffer - cdv - host latency matching (one to nine cells) symmetric tx and rx architecture ? buffer descriptors ? queues user defined field circulates back to the host (32 bits) distributed host or sar-shared memory segmentation simultaneous segmentation and reassembly per-pdu control of clp/pti (ubr) per-pdu control of aal5 uu field message and streaming status modes virtual tx fifo buffer (pci host) multi-queue reassembly processing 32 reassembly queues 64 k vccs maximum * aal5 and aal3/4 cpcs checking aal0 ? pti termination ? cell count termination early packet discard, based on: ? receive buffer underflow ? receive status overflow ? clp with priority threshold ? aal5 max pdu length ? rx fifo buffer full ? frame relay de with priority threshold ? lecid filtering and echo suppression ? per-vcc firewalls dynamic channel lookup (nni or uni addressing) ? supports full address space ? deterministic ? flexible vci count per vpi ? optimized for signalling address assignment message and streaming status modes raw cell mode (52 octet) 200 mbps half duplex 155 mbps full duplex (w/ 2-cell pdus) distributed host or sar-shared memory reassembly eight programmable reassembly hardware time-outs (per-vcc assignable) global max pdu length for aal5 per-vcc buffer firewall (memory usage limit) simultaneous reassembly and segmentation idle cell filtering high performance host architecture with buffer isolation write-only control and status read multiple command for data transfer up to 32 host clients control and status queues physical or logical clients ? enables peer-to-peer architecture descriptor-based buffer chaining scatter/gather dma endian neutral (allows data word and control word byte swapping, for both big and little endian systems) non-word (byte) aligned host buffer addresses automatically detects presence of tx data or rx free buffers virtual fifo buffers (pci bursts treated as a single address) hardware indication of bom allows isolation of system resources status queue interrupt delay designer toolkit evaluation hardware and software reference schematics hardware programming interface-rs823xhpi reference source code (c) ? continued ? 28236-DSH-001-B mindspeed technologies ? ? continued distinguishing features ? generous implementation of oam-pm protocols detection of all f4/f5 oam flows internal pm monitoring and generation for up to 128 vccs optional global oam rx/tx queues in-line oam insertion and generation standards-based i/o 33 mhz pci 2.1 (to 40 mhz) serial eeprom to store pci configuration information phy interfaces ? utopia master (level 1) ? utopia slave (level 1) ? utopia master (level 2) ? utopia slave (level 2) flexible sar-shared memory architecture optional local control interface boundary scan for board-level testing source loopback, for diagnostics glueless connection to mindspeed ? s atm physical layer device, the rs825x and bt8223 standards compliance uni/nni 3.1 tm 4.0/tm4.1 bellcore gr-1248 atm forum b-ici v2.0 28236-DSH-001-B mindspeed technologies ? 28236-DSH-001-B mindspeed technologies ? 7 table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 7 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-19 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.0 cn8236 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 service-specific performance accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 designer toolkit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 2.0 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 high performance host architecture with buffer isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1 multiple atm clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.2 cn8236 queue structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3 buffer isolation utilizing descriptor-based buffer chaining . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4 status queue relation to buffers and descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5 write-only control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.6 scatter/gather dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3 automated segmentation engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4 automated reassembly engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.5 advanced xbr traffic management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5.1 cbr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.2 vbr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.3 abr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.4 ubr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.5 gfr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 table of contents cn8236 atm servicesar plus with xbr traffic management 8 mindspeed technologies ? 28236-DSH-001-B 2.5.6 xbr cell scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.5.7 abr flow control manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.6 burst fifo buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.7 implementation of oam-pm protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.8 standards-based i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.9 electrical/mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.10 logic diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 3.0 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 multiple client architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.1 logical clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.2 resource allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.3 resource isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.4 peer-to-peer transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.5 local processor clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3 write-only control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1 write-only control queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1.1 control variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.1.2 queue management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.1.3 underflow conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.2 write-only status queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.2.1 control variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.2.2 queue management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.2.3 overflow conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.2.4 status queue interrupt delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 4.0 segmentation coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 segmentation functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 segmentation vccs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.1 segmentation vcc table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.2 vcc identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 submitting segmentation data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.1 user data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.2 buffer descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.3 host linked segmentation buffer descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.2.4 transmit queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 cn8236 table of contents atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 9 4.2.2.5 partial pdus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.2.6 virtual paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.3 cpcs-pdu processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.3.1 aal5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.3.2 aal3/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.2.3.3 aal0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.4 atm phy layer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.4.1 head-of-line flushing (holf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.5 status reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.2.6 virtual fifo buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3 segmentation control and data structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.1 segmentation vcc table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.2 data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.3.3 segmentation buffer descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.3.4 transmit queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.3.4.1 entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.3.4.2 transmit queue management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4.3.5 routing tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 4.3.6 segmentation status queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4.3.6.1 entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4.3.6.2 status queue management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.3.6.3 status queue overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.3.7 segmentation internal sram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 5.0 reassembly coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 reassembly functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1 reassembly vccs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1.1 relation to segmentation vccs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.2 channel lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.2.1 programmable block size for vcc table/ vci index table . . . . . . . . . . . . . . . . . . 5-4 5.2.2.2 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.2.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.2.4 aal3/4 lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.2.2.5 variable vpi/port_id lookup (multi-phy support) . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 cpcs-pdu processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.1 aal5 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.1.1 aal5 com processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.1.2 aal5 eom processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.1.3 aal5 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.2 aal3/4 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.3.2.1 aal3/4 per-cell processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.3.2.2 aal3/4 additional bom/ssm processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3.2.3 aal3/4 additional com processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 table of contents cn8236 atm servicesar plus with xbr traffic management 10 mindspeed technologies ? 28236-DSH-001-B 5.3.2.4 aal3/4 additional eom/ssm processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.2.5 aal3/4 mib counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.3 aal0 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.3.1 termination methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.3.2 aal0 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.4 atm header processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.5 bom synchronization signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.5.1 prepend index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.4 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.4.1 host vs. local reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.4.2 scatter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.4.3 free buffer queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.4.4 linked data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.4.5 initialization of buffer structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.4.5.1 buffer descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.4.5.2 free buffer queue base table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.4.5.3 free buffer queue entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.4.5.4 other initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.4.6 buffer allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.4.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.4.8 early packet discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4.8.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4.8.2 frame relay packet discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4.8.3 clp packet discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4.8.4 lane-lecid packet discard ? echo suppression on multicast data frames . . . 5-25 5.4.8.5 dma fifo buffer full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.4.8.6 aal3/4 early packet discard processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.4.8.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.4.9 hardware pdu time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.9.1 reassembly time-out process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.9.2 halting time-out processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.9.3 timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.9.4 reassembly time-out condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.9.5 time-out period calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.10 virtual fifo buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.10.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.10.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.10.3 errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.11 firewall functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.3 credit return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 cn8236 table of contents atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 11 5.5 global statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.6 status queue operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.6.1 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.6.1.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.6.1.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5.6.1.3 errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5.6.1.4 host detection of status queue entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5.6.2 status queue overflow or full condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.7 reassembly control and data structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.7.1 channel lookup structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.7.2 reassembly vcc table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5.7.2.1 aal5, aal0 and aal3/4 vcc table entries . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5.7.2.2 aal3/4 head vcc table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 5.7.3 reassembly buffer descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.7.4 free buffer queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.7.5 reassembly status queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 5.7.6 lecid table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 5.7.7 global time-out table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5.7.8 reassembly internal sram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 6.0 traffic management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 xbr cell scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.2 abr flow control manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2 xbr cell scheduler functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.1 scheduling priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.1.1 16 priority levels + cbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.1.2 vcc priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.2 dynamic schedule table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.2.2 schedule table slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.2.2.3 schedule slot formats without use_sch_ctrl asserted . . . . . . . . . . . . . . . . 6-10 6.2.2.4 schedule slot formats with use_sch_ctrl asserted . . . . . . . . . . . . . . . . . . 6-12 6.2.2.5 some scheduling scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.2.3 cbr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.2.3.1 cbr rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.2.3.2 available rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.2.3.3 cbr cell delay variation (cdv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.2.3.4 cbr channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.2.4 vbr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.4.1 mapping cn8236 vbr service categories to tm 4.1 vbr service categories . . 6-19 6.2.4.2 rate-shaping vs. policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.4.3 single leaky bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 table of contents cn8236 atm servicesar plus with xbr traffic management 12 mindspeed technologies ? 28236-DSH-001-B 6.2.4.4 dual leaky bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.4.5 clp-based buckets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.2.4.6 rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.2.4.7 real-time vbr and cdv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.2.5 ubr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.2.6 xbr tunnels (pipes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.2.7 guaranteed frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.2.8 pcr control for priority queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.3 abr flow control manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.3.1 a brief overview of tm 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.3.2 internal abr feedback control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.3.2.1 source flow control feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6.3.2.2 destination behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.3.2.3 out-of-rate cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.3.3 source and destination behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.3.4 abr vcc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.3.5 abr templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.3.6 cell type decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.3.6.1 in-rate cell streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.3.6.2 abr cell decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.3.7 rate decisions and updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.7.1 abr traffic shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.7.2 rate adjustment overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.7.3 backward rm cell flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.7.4 forward rm cell transmission decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6.3.7.5 acr change notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6.3.7.6 rate adjustment in turnaround rm cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6.3.7.7 optional rate adjustment due to use-it-or-lose-it behavior . . . . . . . . . . . . . . 6-40 6.3.8 boundary conditions and out-of-rate rm cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6.3.8.1 calculated rate boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6.3.8.2 out-of-rate forward rm cell generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6.3.8.3 out-of-rate backward rm cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6.4 gfc flow control manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 6.4.1 a brief overview of gfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 6.4.2 the cn8236 ? s implementation of gfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 6.4.2.1 configuring the link for gfc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 6.5 traffic management control and status structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.1 schedule table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2 cbr-specific structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2.1 cbr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2.2 tunnel traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.5.2.3 sch_state fields for cbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 6.5.3 vbr-specific structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6.5.3.1 vbr sch_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 cn8236 table of contents atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 13 6.5.3.2 vbr1 or vbr2 schedule state table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6.5.3.3 bucket table for vbr2 and vbrc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.5.4 gfr-specific structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6.5.4.1 gfr schedule state table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6.5.4.2 gfr mcr limit bucket table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6.5.5 abr-specific structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6.5.5.1 abr schedule state table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6.5.6 abr instruction tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 6.5.7 rs_queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 6.5.8 scheduler internal sram registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 7.0 oam functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 7.1 oam overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 oam functions supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.2 oam flows supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.2.1 f4 oam flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.2.2 f5 oam flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.2.3 performance monitoring (pm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.1.3 oam cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.1.4 local vs. host processing of oam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2 segmentation of oam cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.1 key oam-related fields for oam segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.1.1 segmentation buffer descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.1.2 low latency transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.1.3 segmentation status queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.1.4 f4 flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.2 error condition during oam segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3 reassembly of oam cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.1 key oam-related fields for oam reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.1.1 reassembly vcc state table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.1.2 reassembly status queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.1.3 f4 flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2 oam reassembly operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.3 error conditions during oam reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.4 pm processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.1 initializing pm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.4.2 setting up channels for pm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.3 pm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.3.1 generation of forward monitoring pm cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.3.2 reassembly of forward monitoring pm cells . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.3.3 reassembly of backward reporting pm cells . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.3.4 turnaround and segmentation of backward reporting pm cells . . . . . . . . . . . . 7-14 7.4.3.5 turnaround of backward reporting pm cells only . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.4 error conditions during pm processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.5 pass_oam function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 table of contents cn8236 atm servicesar plus with xbr traffic management 14 mindspeed technologies ? 28236-DSH-001-B 7.5 oam control and status structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.5.1 seg_pm structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.5.2 rsm_pm table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 8.0 dma coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 dma read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.3 dma write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.4 misaligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.5 control word transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 9.0 local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 memory bank characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3 memory size analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 10.0 local processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 interface pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 bus cycle descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.3.1 single read cycle, zero wait state example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.3.2 single read cycle, wait states inserted by memory arbitration . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.3 double read burst with processor wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.3.4 single write with one-wait-state memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.5 quad write burst, no wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.4 processor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.5 local processor operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.6 standalone operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.6.1 microprocessor interface for multiple physical devices . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10.7 system clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10.8 real-time clock alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10.9 cn8236 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 11.0 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 unimplemented pci bus interface functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3 pci configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4 pci bus master logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5 burst fifo buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 cn8236 table of contents atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 15 11.6 pci bus slave logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.7 byte swapping of control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.8 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.9 interface module to serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.9.1 eeprom format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.9.2 loading the eeprom data at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.9.3 accessing the eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.9.4 using the subsystem id without an eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.10 pci host address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 12.0 atm utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1 overview of atm utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 atm utopia interface logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.3 atm physical i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3.1 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.4 utopia level 2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.4.1 cell tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.4.2 utopia configuration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.4.3 utopia level 2 multi-port operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12.5 utopia level 1 mode cell handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.6 utopia level 1 mode octet handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.7 slave level 1 utopia mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12.8 loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.9 receive cell synchronization logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.10 transmit cell synchronization logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 13.0 aalx interworking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1 aalx rsm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2 aalx seg operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.1 aalx network centric operation ? (external_sch = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.2 aalx voice centric operation ? (external_sch = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 14.0 cn8236 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.3 segmentation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.4 scheduler registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.4.1 0xc4 ? pcr queue interval 2 and 3 register (pcr_que_int23) . . . . . . . . . . . . . . . . . . . 14-18 14.5 reassembly registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 table of contents cn8236 atm servicesar plus with xbr traffic management 16 mindspeed technologies ? 28236-DSH-001-B 14.6 counters and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.6.1 host interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.6.2 local processor interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34 14.7 pci bus interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39 15.0 sar initialization?example tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1 segmentation initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 segmentation control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.2 segmentation internal memory control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.3 segmentation sar shared memory control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2 scheduler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.1 scheduler control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.2 scheduler internal memory control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.2.3 scheduler sar shared memory control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3 reassembly initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.3.1 reassembly control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.3.2 reassembly internal memory control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.3.3 reassembly sar shared memory control structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.4 general initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.4.1 general control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 16.0 electrical and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 pci bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.2 atm physical interface timing ? utopia and slave utopia . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.1.3 system clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.1.4 cn8236 memory interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16.1.5 phy interface timing (standalone mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.1.6 local processor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 16.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 16.4 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 appendix a:boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.2 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.3 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.4 boundary scan register cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 a.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-13 cn8236 table of contents atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 17 a.6 boundary scan description language (bsdl) file a-15 appendix b: list of acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 table of contents cn8236 atm servicesar plus with xbr traffic management 18 mindspeed technologies ? 28236-DSH-001-B cn8236 list of figures atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 19 list of figures figure 1-1. cn8236 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 figure 2-1. multiple client architecture supports up to 32 clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 figure 2-2. cn8236 queue architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-3. interaction of queues with cn8236 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 figure 2-4. reassembly buffer isolation ? data buffers separated from descriptors . . . . . . . . . . . . . . 2-6 figure 2-5. segmentation buffer isolation ? data buffers separated from descriptors . . . . . . . . . . . . . 2-7 figure 2-6. segmentation status queues related to data buffers and descriptors . . . . . . . . . . . . . . . . 2-8 figure 2-7. reassembly status queues related to data buffers and descriptors . . . . . . . . . . . . . . . . . 2-9 figure 2-8. write-only control and status architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 0 figure 2-9. multi-level model for prioritizing segmentation traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 figure 2-10. data fifo buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 figure 2-11. cn8236 logic diagram (1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26 figure 3-1. client/server model of the cn8236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 figure 3-2. peer-to-peer vs. centralized memory data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 figure 3-3. out-of-band control architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 figure 3-4. write-only control queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 figure 3-5. write-only status queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 figure 4-1. segmentation vcc table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 figure 4-2. segmentation buffer descriptor chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 5 figure 4-3. before sar transmit queue entry processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 figure 4-4. after sar transmit queue entry processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 figure 4-5. aal5 cpcs-pdu generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 figure 4-6. aal3/4 cpcs-pdu generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 figure 4-7. route tag table for tag_size = 1 through 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 5 figure 4-8. route tag table for tag_size = 5 through 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 6 figure 4-9. route tag table for tag_size = 9 through 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 figure 5-1. reassembly ? basic process flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 figure 5-2. reassembly vcc table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 figure 5-3. direct index method for vpi/vci channel lookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-4. programmable block size alternate direct index method . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 figure 5-5. direct index lookup method for aal3/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 7 figure 5-6. vpi index table with multiple ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-7. cpcs-pdu reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 figure 5-8. aal5 eom cell processing ? fields to status queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 figure 5-9. aal5 processing ? crc and pdu length checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 figure 5-10. aal3/4 cpcs ? pdu reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 figure 5-11. aal0 pti pdu termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 figure 5-12. host and sar-shared memory data structures for scatter method . . . . . . . . . . . . . . . . . 5-19 figure 5-13. free buffer queue structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 list of figures cn8236 atm servicesar plus with xbr traffic management 20 mindspeed technologies ? 28236-DSH-001-B figure 5-14. data buffer structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 figure 5-15. data structure locations for status queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 2 figure 5-16. status queue structure format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 figure 5-17. vpi/vci channel lookup structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-37 figure 5-18. reassembly vcc table entry lookup mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 figure 5-19. lecid table, illustrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 figure 6-1. non-abr cell scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 figure 6-2. abr flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 figure 6-3. schedule table with size = 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 figure 6-4. schedule slot formats with use_sch_ctrl not asserted . . . . . . . . . . . . . . . . . . . . . . . 6-11 figure 6-5. schedule slot formats with use_sch_ctrl asserted . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 figure 6-6. one possible scheduling priority scheme with the cn8236 . . . . . . . . . . . . . . . . . . . . . . . 6-13 figure 6-7. assigning cbr cell slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 figure 6-8. introduction of cdv at the atm/phy layer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 figure 6-9. schedule table with slot conflicts at different cbr rates . . . . . . . . . . . . . . . . . . . . . . . . 6-16 figure 6-10. cdv caused by schedule table size at certain cbr rates . . . . . . . . . . . . . . . . . . . . . . . . 6-17 figure 6-11. another possible scheduling priority scheme with the cn8236 . . . . . . . . . . . . . . . . . . . . 6-22 figure 6-12. abr service category feedback control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 4 figure 6-13. cn8236 abr-er feedback loop (source behavior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 figure 6-14. cn8236 abr-er feedback generation (destination behavior) . . . . . . . . . . . . . . . . . . . . . 6-26 figure 6-15. steady state abr-er cell stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 figure 6-16. cell type interleaving on abr-er cell stream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 figure 6-17. cell decision table for nrm = 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 figure 6-18. backward_rm flow control, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 figure 6-19. rr rate_index candidate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 4 figure 6-20. er rate_index candidate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 35 figure 6-21. dynamic traffic shaping from rm cell feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 figure 6-22. er reduction mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 figure 6-23. abr linkage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58 figure 6-24. head and tail pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 figure 7-1. oam cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 figure 7-2. functional blocks for pm segmentation and reassembly. . . . . . . . . . . . . . . . . . . . . . . . . 7-11 figure 8-1. little endian aligned transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 figure 8-2. little endian misaligned transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 figure 8-3. big endian aligned transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 figure 8-4. big endian misaligned transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 figure 9-1. cn8236 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 figure 9-2. 0.5 mb sram bank utilizing by_8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 figure 9-3. 1 mb sram bank utilizing by_16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 figure 10-1. cn8236 ? local processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 figure 10-2. local processor single read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 figure 10-3. local processor single read cycle with arbitration wait states . . . . . . . . . . . . . . . . . . . . 10-7 figure 10-4. local processor double read with wait states inserted . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 figure 10-5. local processor single write with one wait state by_16 sram. . . . . . . . . . . . . . . . . . . . 10-9 figure 10-6. local processor quad write, no wait states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 figure 10-7. i960ca/cf to the cn8236 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-12 cn8236 list of figures atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 21 figure 10-8. cn825x and sar (cn8236) interface (standalone operation) . . . . . . . . . . . . . . . . . . . . 10-15 figure 10-9. cn8236/phy functional timing with inserted wait states . . . . . . . . . . . . . . . . . . . . . . . 10-16 figure 10-10. cn8236/rs825x read/write functional timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 figure 10-11. sar/peak 8 control connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 figure 11-1. eeprom connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 figure 12-1. utopia level 2 receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 figure 12-2. receive timing in utopia level 1 mode with cell handshake . . . . . . . . . . . . . . . . . . . . 12-12 figure 12-3. transmit timing in utopia level 1 mode with cell handshake . . . . . . . . . . . . . . . . . . . 12-13 figure 12-4. receive timing in utopia level 1 mode with octet handshake . . . . . . . . . . . . . . . . . . . 12-14 figure 12-5. transmit timing in utopia level 1 mode with octet handshake . . . . . . . . . . . . . . . . . . 12-15 figure 12-6. receive timing in slave utopia level 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 figure 12-7. transmit timing in slave utopia level 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 figure 12-8. source loopback mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12- 18 figure 16-1. pci bus input timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 figure 16-2. pci bus output timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 figure 16-3. utopia and slave utopia input timing measurement conditions . . . . . . . . . . . . . . . . . 16-5 figure 16-4. utopia and slave utopia output timing measurement conditions . . . . . . . . . . . . . . . . 16-6 figure 16-5. input system clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-8 figure 16-6. output system clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-8 figure 16-7. cn8236 memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 -11 figure 16-8. cn8236 memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6-12 figure 16-9. synchronous phy interface input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 figure 16-10. synchronous phy interface output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 figure 16-11. synchronous local processor input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 figure 16-12. synchronous local processor output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 figure 16-13. local processor read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 figure 16-14. local processor write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 figure 16-15. 388-pin ball grid array package (bga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 -23 figure 16-16. cn8236 pinout configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 figure a-1. test circuitry block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 figure a-2. timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-14 list of figures cn8236 atm servicesar plus with xbr traffic management 22 mindspeed technologies ? 28236-DSH-001-B cn8236 list of tables atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 23 list of tables table 2-1. hardware signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 table 3-1. cn8236 control and status queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5 table 3-2. write-only control queue variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 table 3-3. write-only status queue variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 table 4-1. segmentation pdu delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4-2. aal3/4 cpcs-pdu field generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 4-3. aal3/4 sar-pdu field generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -10 table 4-4. coding of segment type (st) field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10 table 4-5. segmentation vcc table entry ? aal3/4-aal5-aal0 format. . . . . . . . . . . . . . . . . . . . . . . 4-14 table 4-6. segmentation vcc table entry ? aal3/4, 5, and 0 field descriptions . . . . . . . . . . . . . . . . 4-15 table 4-7. segmentation vcc table entry ? virtual fifo buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 table 4-8. segmentation vcc table entry ? virtual fifo buffer format field descriptions . . . . . . . . . 4-17 table 4-9. segmentation buffer descriptor entry format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 table 4-10. misc_data field bit definitions with header_mod bit set . . . . . . . . . . . . . . . . . . . . . . . 4-18 table 4-11. misc_data field bit definitions with rpl_vci bit set. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 table 4-12. misc_data field bit definitions with aal_mode set to aal3/4 . . . . . . . . . . . . . . . . . . . . 4-19 table 4-13. segmentation buffer descriptor field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 table 4-14. transmit queue entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 table 4-15. transmit queue entry field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 table 4-16. transmit queue base table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 table 4-17. transmit queue base table entry field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 table 4-18. maximum txfifo size with routing tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 table 4-19. routing tag cross-reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 table 4-20. segmentation status queue entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-28 table 4-21. segmentation status queue entry field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 table 4-22. segmentation status queue format for acr/er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 table 4-23. status queue entry field descriptions for acr/er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 table 4-24. segmentation status queue base table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 table 4-25. segmentation status queue base table entry field descriptions . . . . . . . . . . . . . . . . . . . . 4-30 table 4-26. segmentation internal sram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 table 5-1. programmable block size values for direct index lookup . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-2. stat output pin values for bom synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 table 5-3. prepend index table format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 table 5-4. normal vpi index table entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -37 table 5-5. vpi index table entry format with en_prog_blk_sx(rsm_ctrl1) enabled . . . . . . . . . 5-37 table 5-6. vpi index table entry descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-38 table 5-7. normal vci index table format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 table 5-8. vci index table format with en_prog_blk_sz (rsm_ctrl1) enabled . . . . . . . . . . . . . 5-38 table 5-9. vci index table descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 list of tables cn8236 atm servicesar plus with xbr traffic management 24 mindspeed technologies ? 28236-DSH-001-B table 5-10. reassembly vcc table entry format ? aal5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 table 5-11. reassembly vcc table entry format ? aal0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 table 5-12. reassembly vcc table entry format ? aal3/4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 table 5-13. reassembly vcc table descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 table 5-14. aal3/4 head vcc table entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -46 table 5-15. aal3/4 head vcc table descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 table 5-16. reassembly buffer descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -49 table 5-17. reassembly buffer descriptor structure definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 table 5-18. free buffer queue base table entry format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 49 table 5-19. free buffer queue base table entry descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 table 5-20. free buffer queue entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 table 5-21. free buffer queue entry descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-50 table 5-22. reassembly status queue base table entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 table 5-23. reassembly status queue base table entry descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 table 5-24. reassembly status queue entry format with fwd_pm = 0 . . . . . . . . . . . . . . . . . . . . . . . . 5-51 table 5-25. reassembly status queue entry format with fwd_pm = 1 . . . . . . . . . . . . . . . . . . . . . . . . 5-52 table 5-26. reassembly status queue entry format with fwd_pm = 0 and aal34 = 1 . . . . . . . . . . . . 5-52 table 5-27. pdu_checks field bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 table 5-28. pdu_checks field bits with cnt_rovr = 1 and aal34 = 1. . . . . . . . . . . . . . . . . . . . . . . 5-52 table 5-29. status field bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 table 5-30. stm field bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 table 5-31. reassembly status queue entry descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 table 5-32. lecid table entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 table 5-33. lecid table field definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 table 5-34. global time-out table entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-56 table 5-35. global time-out table entry descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -56 table 5-36. reassembly internal sram memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 table 6-1. atm service category parameters and attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-2. scheduler clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 table 6-3. selection of schedule table slot size by system requirements . . . . . . . . . . . . . . . . . . . . . . 6-9 table 6-4. cn8236 vbr to tm 4.1 vbr mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 table 6-5. abr cell type decision vector (acdv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 0 table 6-6. schedule slot entry ? cbr/tunnel traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 table 6-7. cbr_tun_id field, bit definitions ? cbr slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 table 6-8. cbr_tun_id field, bit definitions ? tunnel slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 table 6-9. schedule slot field descriptions ? cbr traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 table 6-10. sch_state for sch_mode = cbr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 table 6-11. cbr sch_state field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -45 table 6-12. sch_state for sch_mode = vbr1 or vbr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 table 6-13. vbr1 and vbr2 sch_state field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 table 6-14. bucket table entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 table 6-15. bucket table entry field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-48 table 6-16. sch_state for sch_mode = gfr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 table 6-17. sch_state field descriptions for sch_mode = gfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 table 6-18. gfr mcr limit bucket table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 table 6-19. gfr mcr bucket table entry field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 cn8236 list of tables atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? 25 table 6-20. sch_state for sch_mode = abr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 table 6-21. abr sch_state field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -52 table 6-22. abr cell decision block (acdb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 table 6-23. abr cell type actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 table 6-24. abr cell type decision vector (acdv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -55 table 6-25. abr rate decision block (ardb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-56 table 6-26. ardb field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 table 6-27. abr rate decision vector (ardv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 table 6-28. exponent table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 table 6-29. exponent table field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 table 6-30. rs_queue entry ? oam-pm reporting information ready for transmission . . . . . . . . . . 6-59 table 6-31. rs_queue entry ? forward er rm cell received . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 table 6-32. rs_queue entry ? backward er rm cell received . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 table 6-33. rs_queue field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 table 6-34. scheduler internal sram memory map (head/tail pointers) . . . . . . . . . . . . . . . . . . . . . . . 6-60 table 7-1. oam functions of the atm layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 table 7-2. vci values for f4 oam flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 table 7-3. pti values for f5 oam flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 table 7-4. oam type and function type identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 table 7-5. pm-oam field initialization for any pm_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 table 7-6. seg_pm structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 table 7-7. seg_pm field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 table 7-8. rsm_pm table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 table 7-9. rsm_pm table field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 table 9-1. memory bank size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 table 9-2. memory size in bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 table 10-1. processor interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 table 10-2. standalone interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 table 11-1. eeprom fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 table 12-1. atm physical interface mode select (frcfg[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 table 12-2. atm physical interface mode select (utopia1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 table 12-3. utopia mode signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 table 12-4. slave utopia mode interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 table 12-5. cell format 8 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 table 12-6. cell format 16 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 table 12-7. cell format, tagging enabled, 8 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2-8 table 12-8. cell format, tagging enabled, 16 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -9 table 13-1. seg_vcc_index format table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2 table 13-2. rsm_route_tag format table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3-2 table 14-1. type abbreviation description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 table 14-2. cn8236 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 table 14-3. 0x1c0 ? host processor interrupt status register 0 (host_istat0) . . . . . . . . . . . . . . . . 14-30 table 14-4. 0x1c4 ? host processor interrupt status register 1 (host_istat1) . . . . . . . . . . . . . . . . 14-31 table 14-5. 0x1d0 ? host interrupt mask register 0 (host_imask0) . . . . . . . . . . . . . . . . . . . . . . . . 14-32 table 14-6. 0x1d4 ? host interrupt mask register 1 (host_imask1) . . . . . . . . . . . . . . . . . . . . . . . . 14-33 table 14-7. 0x1e0 ? local processor interrupt status register 0 (lp_istat0). . . . . . . . . . . . . . . . . . 14-35 list of tables cn8236 atm servicesar plus with xbr traffic management 26 mindspeed technologies ? 28236-DSH-001-B table 14-8. 0x1e4 ? local processor interrupt status register 1 (lp_istat1). . . . . . . . . . . . . . . . . . 14-36 table 14-9. 0x1f0 ? local processor interrupt mask register 0 (lp_imask0) . . . . . . . . . . . . . . . . . . 14-37 table 14-10. 0x1f4 ? local processor interrupt mask register 1 (lp_imask1) . . . . . . . . . . . . . . . . . . 14-38 table 14-11. pci configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39 table 14-12. pci register configuration register field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40 table 14-13. pci command register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42 table 14-14. pci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-42 table 14-15. pci special status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-43 table 14-16. eeprom register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-43 table 15-1. table of values for segmentation control register initialization . . . . . . . . . . . . . . . . . . . . . 15-1 table 15-2. table of values for segmentation internal memory initialization. . . . . . . . . . . . . . . . . . . . . 15-2 table 15-3. table of values for segmentation sar shared memory initialization . . . . . . . . . . . . . . . . . 15-3 table 15-4. table of values for scheduler control register initialization . . . . . . . . . . . . . . . . . . . . . . . . 15-5 table 15-5. table of values for sch sar shared memory initialization . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 table 15-6. table of values for reassembly control register initialization . . . . . . . . . . . . . . . . . . . . . . 15-8 table 15-7. table of values for reassembly internal memory initialization . . . . . . . . . . . . . . . . . . . . . 15-10 table 15-8. table of values for reassembly sar shared memory initialization. . . . . . . . . . . . . . . . . . 15-11 table 15-9. table of values for general control register initialization . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 table 16-1. pci bus interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 table 16-2. utopia interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 table 16-3. slave utopia interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 table 16-4. system clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 table 16-5. sram organization loading dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 table 16-6. sar shared memory output loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 table 16-7. cn8236 memory interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 -10 table 16-8. phy interface timing (procmode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 table 16-9. synchronous processor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 table 16-10. local processor memory interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 6 table 16-11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 table 16-12. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 table 16-13. pin description (numeric list) (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25 table 16-14. pin description (alphabetic list) (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-29 table 16-15. spare pins reserved for inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 table a-1. boundary scan signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 table a-2. ieee std. 1149.1 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 table a-3. boundary scan register cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 table a-4. timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-13 28236-DSH-001-B mindspeed technologies ? 1-1 1 1.0 cn8236 product overview 1.1 introduction the cn8236 service segmentation and reassembly controller ( servicesar ) delivers a wide range of advanced atm, aal, and service-specific features in a highly integrated cmos package. some of the cn8236 service-level features provide system designers with capabilities of accelerating specific protocol interworking functions. these features include, for example, virtual fifo buffer segmentation of circuit-based constant bit rate (cbr) traffic and frame relay early packet discard (epd) based on the discard eligibility (de) field. other service-level functions enable network level functionality or topologies. two examples of these features include generic flow control (gfc) and echo suppression of multicast data frames on emulated lan (elan) channels. in addition to meeting the requirements contained in uni 3.1 , the cn8236 complies with atm forum traffic management specification, tm 4.1 . the cn8236 provides traffic shaping for all service categories: ? cbr, variable bit rate (vbr)?both single and dual leaky bucket unspecified bit rate (ubr) available bit rate (abr) gfc?both controlled and uncontrolled flows guaranteed frame rate (gfr), that is, guaranteed minimum cell rate (mcr) on ubr virtual channel connections (vccs) the internal xbr traffic manager automatically schedules each vcc according to user assigned parameters. the cn8236?s architecture is designed to minimize and control host traffic congestion. the host manages the cn8236 terminal with an efficient architecture that uses write-only control and status queues. for example, the host submits data for transmit by writing buffer descriptor pointers to one of 32 transmit queues. these entries can be thought of as task lists for the service sar to perform. the cn8236 reports segmentation and reassembly status to the host by writing entries to segmentation and reassembly status queues, which the host then further processes. this architecture lessens the control burden on the host system and minimizes peripheral component interconnect (pci) bus utilization by eliminating reads across the pci bus from host control activities. 1.0 cn8236 product overview cn8236 1.1 introduction atm servicesar plus with xbr traffic management 1-2 mindspeed technologies ? 28236-DSH-001-B the cn8236 host interface provides for control of host congestion through the following mechanisms. first, each peer maintains separate control and status queues. then, each vcc in a peer group can be limited to a specific maximum receive buffer utilization, further controlling congestion. epd is supported for vccs that exceed their resource allotments. on transmit, peers are assigned fixed or round-robin priority to ensure predictable servicing. the host can implement a congestion notification algorithm for abr with a simple one-word write to a sar control register. the sar reduces the explicit rate (er) field or sets the congestion indication (ci) bit in turnaround resource management (rm) cells, based on user configuration. the cn8236 consists of five separate coprocessors: incoming dma, outgoing dma, reassembly, segmentation, and xbr traffic manager each coprocessor maintains state information in shared, off-chip memory. this memory is controlled by the sar through the local bus interface, which arbitrates access to the bus between the various coprocessors. although these coprocessors run off the same system clock, they operate asynchronously from each other. communication between the coprocessors takes place through on-chip fifo buffers or through queues in sar-shared memory (that is, memory local to the sar and accessible both to the sar and the host). the cn8236 ? s on-chip coprocessor blocks are surrounded by high performance pci and utopia ports for glueless interface to a variety of system components with full line rate throughput and low bus occupancy. figure 1-1 illustrates these functional blocks. cn8236 1.0 cn8236 product overview atm servicesar plus with xbr traffic management 1.1 introduction 28236-DSH-001-B mindspeed technologies ? 1-3 figure 1-1. cn8236 functional block diagram pci master/slave dma coprocessor reassembly block segmentation block pci clock domain (system clock domain) local bus interface xbr traffic manager (atm phy interface clock domain) (boundary scan clock domain) pci bus master logic drivers pci slave logic control/status registers, counters, and internal sram memory arbiter clock/ timer (32 bit) boundary scan local bus 60 test bus 5 pci bus interface host 50 at m physical receive interface at m physical transmit interface 26 26 reassembly coprocessor dma outgoing channel burst fifo (depth = 64 bytes) segmentation coprocessor tx fifo (depth = program- mable from 1 to 9 cells) xbr scheduler / abr flow control mgr. rx fifo (depth = 256 bytes) physical rx port physical tx port dma incoming channel burst fifo (depth = program- mable 2048 or 8192 bytes) 8236_001 1.0 cn8236 product overview cn8236 1.2 service-specific performance accelerators atm servicesar plus with xbr traffic management 1-4 mindspeed technologies ? 28236-DSH-001-B 1.2 service-specific performance accelerators the cn8236 incorporates several service-specific features, which accelerate system performance. some of these service level features provide the possibility for designers to accelerate specific protocol interworking functions. other service level features enable network level functionality. these features are outlined in chapter 2.0 , and are fully described in succeeding chapters. uni or nni addressing the cn8236 handles both user-network interface (uni) addresses, which use an 8-bit virtual path identifier (vpi) field, and network-to-network interface (nni) addresses, which use a 12-bit vpi field. frame relay interworking the vbr traffic category includes rate-shaping via the dual leaky bucket generic cell rate algorithm (gcra) based on the cell loss priority (clp) bit, for use in frame relay. the cn8236 also implements the frame relay discard attribute by performing early packet discard based on the frame ? s de field and assigned discard priority. ip interworking the cn8236 facilitates atm call control signalling procedures as defined in at m fo r u m ? s uni signalling 4.0 specification (sig 4.0), to support ip over atm environments. some of the sig 4.0 capabilities that are of interest to ip over atm and which the cn8236 allows for are as follows: abr signalling for point-to-point calls traffic parameter negotiation frame discard support guaranteed frame rate the cn8236 can rate-shape atm adaptation layer type 5 (aal5) common part convergence sublayer protocol data units (cpcs-pdus, that is, frames) in the ubr service category, by providing a guaranteed mcr for ubr vccs. early packet discard the epd feature provides a mechanism to discard complete or partial cpcs-pdus based upon service discard attributes or error conditions. the reassembly coprocessor performs epd functions under the following conditions: frame relay packet discard based on the de field in the received frame and the channel exceeding a user-defined priority threshold. packet discard based on the clp bit. lane-lecid packet discard to implement echo suppression on multicast data frames on elan channels. packet discard when a firewall condition occurs on a vcc or group. receive fifo buffer full condition/threshold. various aal3/4 management information base (mib) errors. cn8236 1.0 cn8236 product overview atm servicesar plus with xbr traffic management 1.2 service-specific performance accelerators 28236-DSH-001-B mindspeed technologies ? 1-5 cbr traffic handling the segmentation coprocessor includes an internal rate-matching mechanism to match the internal rate (the local reference rate) of cbr segmentation to an external rate (the host rate). the user can direct the cn8236 to segment traffic from a fixed pci address (that is, a virtual fifo buffer) for circuit-based cbr traffic. the user can delineate up to sixteen cbr pipes (or tunnels) in which to transmit multiple ubr, vbr, or abr channels. in addition, the bandwidth of any single tunnel can be shared by up to four different priorities of traffic, establishing a multi-service tunnel. this allows proprietary management schemes to operate under preallocated cbr bandwidths. abr traffic management the abr flow control manager dynamically rate-shapes abr traffic independently per vcc, based upon network feedback. one or more abr templates are used to govern the behavior of traffic. both relative rate (rr) and er algorithms are used when computing a rate adjustment on an abr vcc. programmable abr templates allow rate-shaping on groups of vccs to be tuned for different network policies. new per-vcc mcr and icr fields reduce the number of abr templates needed in local memory. the cn8236 allows rate adjustments on turnaround rm cells, based on congestion in the host. the cn8236 allows rate adjustments due to use-it-or-lose-it behavior. the cn8236 generates out-of-rate forward rm cell(s) to restart scheduling of a vcc whose rate has dropped below the schedule table minimum rate. the cn8236 optionally posts the current allowed cell rate (acr) on the segmentation status queue for the host monitoring functions. vbr traffic management the cn8236 schedules each vbr vcc according to gcra parameters stored in the individual vcc control tables. the internal xbr traffic manager schedules the transmitted data to maximize the permitted link utilization. the actual rate sent is accurate to within 0.15% of the negotiated rates over a range from 10 cells per second to full line rate of 155 mbps. three vbr modes are supported: sustained cell rate (one leaky bucket) peak and sustained cell rate (dual leaky bucket) clp 0+1 shaping (supports committed/best effort services) (this is the mode recommended by the internet engineering task force [ietf] as the most convenient model for ip over atm interworking.) virtual path networking the cn8236 can interleave segmentation of numerous vccs (that is, separate vc channels) as members of one virtual path (vp). vp-based traffic shaping is supported. the entire vp is scheduled according to parameters for one vcc. 1.0 cn8236 product overview cn8236 1.2 service-specific performance accelerators atm servicesar plus with xbr traffic management 1-6 mindspeed technologies ? 28236-DSH-001-B aal for proprietary traffic the cn8236 incorporates an aal0 traffic class for both segmentation and reassembly, which acts as an aal level for proprietary use. several options for packetization are implemented. optional local processing of atm management traffic the cn8236 ? s local processor interface allows for an optional local processor to direct segmentation and reassembly of atm management level traffic, such as operations and maintenance (oam) cells, performance monitoring (pm) cells, signalling, and interim local management interface (ilmi) traffic. this off-loads network control traffic from the host, thereby focusing host processing power on the user application. internal snmp mib counters cn8236 has three internal counters that measure cells received, cells discarded, and aal5 pdus discarded (to meet ilmi and rfc1695 requirements). compactpci hot swap circuity and i/o have been added in to functionally comply with the compactpci hot swap specification (picmg 2.1 r1.0 ). refer to sections 7.2 and 3.1.8 of the specification for details of the hot swap operation. the hswitch* input indicates the state of the handle switch. a logic low indicates that the handle is locked, whereas a logic high indicates that the handle is unlocked. the hled* output is a 12 ma open drain capable of driving an led directly. a logic low illuminates the led. the henum* output is an 8 ma open drain in compliance with the enum# signal defined in the compactpci specification. cn8236 1.0 cn8236 product overview atm servicesar plus with xbr traffic management 1.3 designer toolkit 28236-DSH-001-B mindspeed technologies ? 1-7 1.3 designer toolkit the cn8236 atm evaluation environment provides evaluation capability for the cn8236 service sar. this environment serves as a hardware and software reference design for development of customer-specific atm applications. the evaluation hardware and software was designed to provide a rapid prototyping environment to assist and speed customer development of new atm products, thereby reducing product time to market. this environment facilitates the following: rapid customer product development hardware reference design software reference design (based on vxworks) traffic generation and checking capability comprising part of this development environment is the cn8236/8250evm, a pci card specifically designed to be a full-featured atm controller implementing the full functionality of the cn8236 service sar. the cn8236 resides at the heart of this pci card. the pci interface between the host processor and the local system is controlled by mindspeed ? s hardware programming interface (cn823xhpi), a software driver to the cn8236, on top of which a system designer can develop and place proprietary driver software. this interface allows users to easily port their applications to the cn8236. this software is written in c, and source code is available under license agreement. the evaluation environment also includes a full set of design schematics, and artwork for the cn8236evm pci card. 1.0 cn8236 product overview cn8236 1.3 designer toolkit atm servicesar plus with xbr traffic management 1-8 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? 2-1 2 2.0 architecture overview 2.1 introduction the cn8236 service sar architecture efficiently handles high bandwidth throughput across the spectrum of three different atm adaptation layers and all atm service categories. this chapter provides an overview of this architecture. the first section describes the queue and data buffer system. the second section describes the segmentation and reassembly functions from within the context of the queue structures. the last major operational description covers the xbr traffic manager. the remaining sections cover operation and maintenance and performance monitoring (oam/pm), the various device inputs and outputs, and the logic diagram with pin descriptions. this architectural overview serves as a solid foundation for understanding the complete functionality of the cn8236. 2.0 architecture overview cn8236 2.2 high performance host architecture with buffer isolation atm servicesar plus with xbr traffic management 2-2 mindspeed technologies ? 28236-DSH-001-B 2.2 high performance host architecture with buffer isolation once initialized and given a segmentation or reassembly task, the cn8236 operates autonomously. because the cn8236 is a high performance subsystem, the host/ service sar architecture and the algorithms for task submission and status reporting have been optimized to minimize the control burden on the host system. 2.2.1 multiple atm clients the cn8236, functioning as an atm uni, provides a high throughput uplink to a broadband network. most individual atm service users (or clients) do not have the bandwidth requirements to equal the throughput capability of the cn8236. as an application example, atm clients can be ethernet or frame relay ports. therefore, many service clients are typically aggregated onto one atm uni. these clients can have very different needs and/or isolation requirements. in order to fully capitalize on the high bandwidth of this service while meeting per-vcc quality of service (qos) needs, the cn8236 functions as an atm server for up to 32 clients. in this way, the bandwidth requirements of the service user (the client) can be balanced with the service throughput capability of the cn8236 and the rest of the specific system. the cn8236 provides multiple independent control and status communication paths. each communication path, or flow, consists of a control queue and a status queue for both segmentation and reassembly. the host assigns each of these independent flows to system clients, or peers. these can be either phy or logical entities. as throughput requirements escalate, the host system can add processing power in the form of additional peers. this degree of freedom creates a scalable host environment. multiple vccs can be assigned to each client. each client interfaces to the cn8236 independently. due to its server architecture, the cn8236 supplies the synchronization between asynchronous tasks requiring atm services. figure 2-1 illustrates this client/server model. it shows that clients can be multiple applications in a shared memory, or separate phy entities. all communicate directly with the cn8236. cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.2 high performance host architecture with buffer isolation 28236-DSH-001-B mindspeed technologies ? 2-3 2.2.2 cn8236 queue structure the flow of the reassembly, scheduling, and segmentation processes in the cn8236 is monitored, coordinated, and controlled through the use of a full array of circular queues, serviced by the cn8236 or the host. the following queues exist in local memory: transmit queues (up to 32 queues) reassembly/segmentation queue free buffer queues (up to 32 queues) ? includes the global oam free buffer queue. figure 2-2 illustrates the location of each queue. transmit queues are used by the host to submit chains of segmentation buffer descriptors to the cn8236 for segmentation. the segmentation coprocessor then processes these transmit queue entries as part of the segmentation function. the reassembly/segmentation queue is written to by the reassembly coprocessor and read by the segmentation coprocessor. the queue includes data on oam-pm cells to be transmitted and as data on abr-class received backward_rm and forward_rm cells. the rsm/seg queue is a private queue for the sar that the host cannot read or write. figure 2-1. multiple client architecture supports up to 32 clients pci motherboard cn8236 subsystem at m user-network interface atm server host data path host control/status flow legend: pci cards physical client physical client logical client logical client 8236_002 2.0 architecture overview cn8236 2.2 high performance host architecture with buffer isolation atm servicesar plus with xbr traffic management 2-4 mindspeed technologies ? 28236-DSH-001-B the host furnishes data buffers to the reassembly processor by posting their location and availability to the free buffer queues, one of which can be designated as the global oam free buffer queue. the reassembly coprocessor uses the free buffer queue entries to allocate data buffers for received atm cells during reassembly. the following queues exist in host (or optionally, sar-shared) memory: segmentation status queues (up to 32 queues) ? includes the global oam segmentation status queue reassembly status queues (up to 32 queues) ? includes the global oam reassembly status queue the cn8236 reports segmentation status to the segmentation status queues. one of these can be designated as the global oam segmentation status queue. the host further processes these segmentation status queue entries. the cn8236 reports reassembly status to the reassembly status queues. one of these can be designated as the global oam reassembly status queue. the host further processes these reassembly status queue entries. figure 2-2. cn8236 queue architecture sar-shared memory area segmentation function reassembly function rsm/seg queue transmit queues (32) free buffer queues (32) global oam free buffer queue segmentation status queues reassembly status queues (32) host memory area (1) global oam seg status queue global oam rsm status queue reassembly function segmentation function cn8236 note(s): (1) status queues may be optionally placed in sar-shared memory. 8236_096 cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.2 high performance host architecture with buffer isolation 28236-DSH-001-B mindspeed technologies ? 2-5 the queues described above provide the control information that fuels the reassembly and segmentation functions. these queues, placed on asynchronous communication paths, directly associate the host with the cn8236 during processing and associate each of the major functional blocks of the cn8236 with each other. figure 2-3 illustrates these interactions. the arrows indicate which system entity writes to each queue, and which entity reads each queue. figure 2-3. interaction of queues with cn8236 functional blocks legend: segmentation local memory interface block cn8236 pci bus interface transmit queues rsm/seg queue free buffer queues global oam free buffer queue host global oam rsm status queue seg status queues global oam seg status queue xbr scheduler write read reassembly block 8236_003 2.0 architecture overview cn8236 2.2 high performance host architecture with buffer isolation atm servicesar plus with xbr traffic management 2-6 mindspeed technologies ? 28236-DSH-001-B 2.2.3 buffer isolation utilizing descriptor-based buffer chaining the cn8236 uses buffer structures for reassembly and segmentation. the buffer structures maximize the flexibility of the system architecture by isolating the data buffers from the mechanisms that handle buffer allocation and linking. this allows the data buffers to contain only payload data, no control fields or other user fields. the user can store the data buffers separately from the buffer descriptors and implement a minimum data copy architecture. figure 2-4 illustrates how reassembly data buffers and buffer descriptors are chained together and manipulated by the service sar. 1. the host creates a link between a reassembly data buffer and a buffer descriptor by writing in the buffer descriptor entry, a pointer to the data buffer. 2. the host then formats a free buffer queue entry, which includes pointers to both the data buffer and buffer descriptor, and writes this message to the free buffer queue. 3. the reassembly coprocessor reads this free buffer queue entry and uses the pointer to the reassembly data buffer as the memory location to write the pdu being reassembled. 4. as reassembly of that pdu progresses, the reassembly coprocessor chains together the necessary number of additional buffer descriptors (and thus their associated reassembly data buffers) to complete reassembly of the pdu. figure 2-4. reassembly buffer isolation?data buffers separated from descriptors (32) free buffer queues 1 2 3 1 2 3 data buffers rsm buffer descriptors rsm memory cn8236 pci host (or optionally local) memory (read) (write) (write) (write) (sar links buffer descriptors for the pdu.) legend: rsm coprocessor associations (pointing function) data writes host actions sar actions 8236_004 cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.2 high performance host architecture with buffer isolation 28236-DSH-001-B mindspeed technologies ? 2-7 figure 2-5 illustrates how the host submits linked data buffers (that is, pdus) to the transmit queue for segmentation. the process is as follows: 1. the host links the buffer descriptors (in sar-shared memory) for the associated data buffers (in host memory) containing the pdu to be segmented. 2. the host then formats a 2-word transmit queue entry and writes this entry to the transmit queue. the location of the first buffer descriptor in the linked chain is contained in the transmit queue entry. 3. the segmentation coprocessor automatically senses the presence of new transmit queue entries, reads them, and schedules the new data for transmission. the transmit queue acts as a fifo buffer for segmentation task pointers. figure 2-5. segmentation buffer isolation ? data buffers separated from descriptors transmit queues 1 2 3 1 2 3 data buffers seg buffer descriptors host memory seg memory cn8236 pci (read) (read) (write) (write) (read) seg coprocessor legend: associations (pointing function) data reads host actions sar actions 8236_005 2.0 architecture overview cn8236 2.2 high performance host architecture with buffer isolation atm servicesar plus with xbr traffic management 2-8 mindspeed technologies ? 28236-DSH-001-B 2.2.4 status queue relation to buffers and descriptors the status queues employed by the cn8236 are written by the sar and read by the host. these status queue entries provide the data needed by the host in order to further process the segmentation and reassembly data flow in progress or just completed. each status queue entry thus includes data (such as error flags and status bits), which the host uses in its succeeding process steps. the sar also includes, in each status queue entry, a pointer to the first buffer descriptor of the segmented or reassembled data buffer(s) which comprise a single pdu. this accomplishes the other principal function of a status queue entry: to establish the association from the sar to the host of the successful or unsuccessful segmentation or reassembly of a pdu. figure 2-6 illustrates the association between the segmentation status queues and segmentation data buffers and descriptors. the figure shows one three-buffer pdu on a single virtual channel, represented by a single entry in one of the transmit queues and a single entry in one of the seg status queues. the host links the buffer descriptors pointing to the data buffers containing the pdu, makes a host-only copy of the buffer descriptor, then writes the transmit queue entry. the sar performs segmentation processing on the pdu and writes a seg status queue entry informing the host of the status of the segmentation process. figure 2-6. segmentation status queues related to data buffers and descriptors transmit queues host writes transmit queue entry host writes sbd sar writes seg status queue entry seg buffer descriptors seg data buffers seg status queues buffer descriptors (host copy) (buffer descriptors linked by host) host memory pci sar-shared memory legend: associations (pointing function) host actions 8236_006 cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.2 high performance host architecture with buffer isolation 28236-DSH-001-B mindspeed technologies ? 2-9 figure 2-7 illustrates the association between the reassembly status queues and reassembly data buffers and descriptors. the host submits free buffers to the sar by writing pointers to them in the free buffer queue entries. the sar links the buffer descriptors pointing to the three data buffers containing the reassembled pdu, and writes the rsm status queue entry containing the pointer to the first buffer descriptor for that pdu. the host further processes the pdu using that data. figure 2-7. reassembly status queues related to data buffers and descriptors free buffer queues host writesfree buffer queue entry sar writes rsm status queue entry rsm data buffers rsm status queues rsm buffer descriptors (buffer descriptors linked by sar) host memory pci legend: associations (pointing function) sar actions sar-shared memory 8236_007 2.0 architecture overview cn8236 2.2 high performance host architecture with buffer isolation atm servicesar plus with xbr traffic management 2-10 mindspeed technologies ? 28236-DSH-001-B 2.2.5 write-only control/status figure 2-8 illustrates the cn8236 ? s write-only pci control architecture. the host manages the cn8236 atm terminal using write-only control and status queues. this architecture minimizes pci bus utilization by eliminating reads from control activities. pci writes use the bus much more efficiently than pci reads. during a pci write, the bus master can post the write data to an internal fifo buffer in the slave, terminate the transaction, and immediately release the bus. on the other hand, during pci reads, the bus master retrieves the data from the slave while holding the bus. since the data retrieval takes some time, reads increase the pci bus utilization time for each transaction. the cn8236 eliminates read operations except for burst reads to gather segmentation data. 2.2.6 scatter/gather dma the cn8236 ? s direct memory access (dma) coprocessor works in close conjunction with the segmentation and reassembly coprocessors to gain access to the pci bus, transfer the requested data, and notify the segmentation or reassembly coprocessor that the transfer is complete. the dma coprocessor transfers all data using the read and write burst buffers in the pci bus interface. in general, two types of transactions are processed: 12- or 14-word burst accesses for data, or 1- to 4-word accesses for control and status messages. for outgoing messages, the dma coprocessor moves data from host memory to the segmentation coprocessor using a gather dma method. for incoming messages, the dma coprocessor moves data from the reassembly coprocessor to host memory using a scatter dma method. the dma coprocessor can handle transfers from the pci bus with data that is not aligned on word boundaries. it also selectively transfers data to comply with either a big endian or little endian host data structure. figure 2-8. write-only control and status architecture write-only architecture reduces pci utilization dramatically, as reads take many more clock cycles. control rsm data (writes) status seg data (read multiples) host cn8236 pci 8236_008 cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.2 high performance host architecture with buffer isolation 28236-DSH-001-B mindspeed technologies ? 2-11 2.2.7 interrupts the cn8236 informs the host of segmentation and reassembly activity by means of maskable interrupts sent to the host processor, triggered by writes to the segmentation and reassembly status queues. the user can configure the sar to generate these status queue entries and interrupts at pdu boundaries (called message mode), or at data buffer boundaries (called streaming mode). the cn8236 can also be configured with a status queue interrupt delay, which can be enabled in order to reduce the interrupt processing load on the host. this has value when the sar resides in an environment in which the host is not dedicated to data communications processing. 2.0 architecture overview cn8236 2.3 automated segmentation engine atm servicesar plus with xbr traffic management 2-12 mindspeed technologies ? 28236-DSH-001-B 2.3 automated segmentation engine the cn8236 can segment up to 64 k vccs simultaneously. the segmentation coprocessor block independently segments each channel and multiplexes the vccs onto the line with cell level interleaving. for each cell transmission opportunity, the xbr traffic manager tells the segmentation coprocessor which vcc to send. the cn8236 provides full support of the aal5 and aal3/4 protocols and a transparent or null adaptation layer, aal0. each segmentation channel is specified as a single entry in the segmentation vcc table located in sar-shared memory. a vcc specifies a single vc or vp in the atm network. these vcc table entries define the negotiated or contracted characteristics of the traffic for that channel, and are initialized by the host either during system initialization or on-the-fly during operation. an initialized segmentation vcc table entry effectively establishes a connection on which data can be segmented. note: abr vccs occupy two table entries. the host submits data for segmentation by first linking buffer descriptors that point to the buffers containing the pdu to be transmitted, and then submitting that chained message to the sar by writing to one of 32 independent circular transmit queues. the segmentation coprocessor then operates autonomously, formatting the cells on each channel according to the host-defined segmentation vcc table entries for each channel. the formatting functions include the following: the segmentation coprocessor formats the atm cell header for each cell, based on the settings in the segmentation vcc table entry for that vcc. the segmentation coprocessor also generates the cpcs-pdu header and trailer fields in the first and last cell of the segmented pdu. for aal5 traffic, the seg coprocessor also generates the pdu-specific fields in the trailer of the cpcs-pdu, and places these in the last cell (the end of message [eom] cell) for the pdu. each aal3/4 cell carries 44 octets of payload and four octets (in five fields) of header and trailer information. the sar performs the formatting steps necessary to create aal3/4 cells. aal0 is intended for client-proprietary use. for aal0, the segmentation coprocessor segments the service data unit (sdu) to atm cell payload boundaries and generates atm cell headers, but generates no other overhead fields. the user has per-channel, per-pdu control of raw cell mode segmentation, where the segmentation coprocessor reads the entire 52-octet atm cell from the segmentation buffer and does not generate the atm headers for the cells. the formatted cells are passed through the transmit fifo buffer to the phy interface for transmission. cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.3 automated segmentation engine 28236-DSH-001-B mindspeed technologies ? 2-13 the system designer can set the depth of the transmit fifo buffer from one to nine cells deep to optimize the balance between cell delay variation (cdv). this increases with longer transmit fifo buffer depth and pci latency protection, which decreases with shorter transmit fifo buffer depth. the cn8236 provides a method to segment traffic from a fixed pci address (or virtual fifo buffer). this is intended for circuit-based cbr traffic such as voice channels. the cn8236 reports segmentation status to the host on one of a set of 32 independent parallel segmentation status queues. the cn8236 writes segmentation status queue entries on either pdu boundaries or buffer boundaries, selectable on a per-vcc basis. pdu boundary status reporting is called message mode, while buffer status reporting is called streaming mode. 2.0 architecture overview cn8236 2.4 automated reassembly engine atm servicesar plus with xbr traffic management 2-14 mindspeed technologies ? 28236-DSH-001-B 2.4 automated reassembly engine the reassembly coprocessor processes cells received from the atm phy interface block. the coprocessor extracts the aal sdu payload from the received cell stream and reassembles this information into buffers supplied by the host system. each active reassembly channel is specified as a single entry in the reassembly vcc table located in sar-shared memory. one rsm vcc table entry defines the negotiated or contracted characteristics of the reassembly traffic for a particular channel. each table entry is initialized by the host during system initialization, or on-the-fly. the sar uses the rsm vcc table to store temporary information to assist the reassembly process. an initialized reassembly vcc table entry effectively establishes a connection on which the cn8236 can reassemble data. using a dynamic channel directory lookup method, the cn8236 reassembles up to 64 k vccs simultaneously at a maximum rate of 200 mbps on simplex connections and 155 mbps on full-duplex connections. the channel directory mechanism allows flexible preallocation of resources and provides deterministic channel identification over the full uni or nni virtual path identifier/virtual channel identifier (vpi/vci) address space. the total number of vccs supported is limited by the memory allocated to the rsm vcc table and the channel directory. the reassembly coprocessor extracts the aal sdu payload from the received cell stream and reassembles this information into system buffers allocated per-vcc. the cn8236 supports aal5, aal3/4, and aal0 reassembly and 52-octet raw cell mode. for aal5, the reassembly coprocessor extracts and checks all pdu protocol overhead. for aal3/4, the reassembly coprocessor performs all error detection and checking procedures incorporated in aal3/4, and reassembles sdus based on message id (mid). the cn8236 provides two methods of terminating an aal0 pdu: 1. payload type identifier (pti) termination, where the pti bit in the cell header is monitored for the end of message (eom) cell indication. 2. cell count termination, where the cn8236 terminates the pdu when a user-defined number of cells have been received on that channel. the aal0 pdu termination method is selectable on a per-vcc basis. the user can, on a per-channel basis, establish raw cell mode reassembly. in this mode the header error check (hec) octet is deleted to align the 53-octet cell to 32-bit boundaries, and the rsm coprocessor reassembles the entire 52-octet atm cell into the reassembly buffer. cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.4 automated reassembly engine 28236-DSH-001-B mindspeed technologies ? 2-15 the cn8236 provides the user with generous per-channel control of the reassembly process, including the following: assignment of priorities for reassembly buffer return processing. cell filtering on inactive channels. mechanisms to establish per-vcc firewalling by allocating buffer credits on a per-channel basis. (this limits the possibility of one vcc consuming all of the memory resources.) per-vcc activation and control of a background hardware time-out function where the user selects one of eight programmable time-out periods. (the background function then automatically detects partially reassembled pdus and reports this status to the host so that these buffers can be recovered and re-allocated.) per-vcc monitoring of the length of the reassembled pdu, with status reporting if the length exceeds a set maximum length for that channel. the cn8236 implements an early packet discard feature to enable discarding of complete or partial cpcs-pdus based upon service discard attributes or error conditions. the early packet discard function halts reassembly of the cpcs-pdu marked for discard until the next beginning of message (bom) cell and/or the error condition has cleared. the sar writes a status queue entry with the appropriate status flags set, which indicate the reason for the discard. this function can be enabled for the following conditions: frame relay discard based on the frame ? s de setting and the channel exceeding a user-defined priority threshold. clp packet discard based on the received cell ? s clp bit setting and exceeding channel priority threshold. lane-lecid packet discard on elan channels, which implements echo suppression on multicast data frames. early packet discard on aal5 channels when the reassembled pdu length exceeds the user-defined maximum pdu length for that vcc. early packet discard on channels encountering a free buffer queue empty (underflow) condition (meaning there are no available buffers in the free buffer queue that channel is assigned to). early packet discard on pdus when a dma incoming fifo buffer full condition occurs. early packet discard on channels encountering a reassembly status queue full (overflow) condition. early packet discard on aal3/4 channels with these mib errors: st_err (segment type error), sn_err (sequence number error), and li_err (sar-pdu length error). the system designer can set the reassembly status reporting for any channel to either message mode or streaming mode. in message mode, a status entry is written only when the last buffer in a message completes reassembly. in streaming mode, a status entry is written for each buffer as it completes reassembly. 2.0 architecture overview cn8236 2.5 advanced xbr traffic management atm servicesar plus with xbr traffic management 2-16 mindspeed technologies ? 28236-DSH-001-B 2.5 advanced xbr traffic management the cn8236 implements atm ? s inherent robust traffic management capabilities for cbr, vbr, abr, ubr, gfr, and gfc. the cn8236 manages each vcc independently and dynamically. the user assigns each connection a service class, a priority level, and a rate if applicable. then, the on-chip traffic controller, the xbr traffic manager, optimizes use of the line bandwidth according to the vcc ? s traffic parameters and control information stored in sar-shared memory. the xbr traffic manager guarantees the compliance of each vcc to its service contract with the atm network at the uni ingress point. it schedules all data traffic by acting as a master to the segmentation coprocessor. one of the functional components of the xbr traffic manager is the xbr scheduler. the xbr traffic manager assigns segmentation traffic from active vccs to schedule slots, which the segmentation coprocessor then complies to by segmenting vcc traffic in the sequence/schedule dictated by the xbr scheduler. in addition to reserved cbr bandwidth, the cn8236 provides 16 segmentation priorities. the user configures these priorities for the remaining service categories, including the tm 4.1 -defined abr class. the cn8236 ? s xbr traffic manager implements multiple functional levels of traffic prioritizing. this is illustrated in figure 2-9 . the host submits data to be sent by writing entries to the transmit queues for segmentation. the sar processes these transmit queues either in round ? robin order (transmit queue 0 through 31, looped back to 0), or in priority order (with transmit queue 31 having highest priority). this scheme gives the user or system designer some control of the delay between the host submitting traffic and the sar starting to process that traffic. for instance, the user could assign cbr traffic to the highest priority transmit queue in order to minimize any delay in processing and scheduling that traffic. the cn8236 then submits this traffic demand to the xbr traffic manager for scheduling. traffic is scheduled based on the traffic class plus certain parameters from the segmentation vcc table entries (primarily the gcra i and l parameters). and if the service category is abr, the sar also uses certain parameters from the abr templates to help determine that traffic ? s placement on the schedule table. the conforming traffic to be transmitted is further groomed in internal priority queues. each virtual channel is prioritized according to its assigned scheduling priority. cbr channels are given pre-assigned segmentation bandwidth, and channels for the remaining service categories scheduled according to their priority number (priority 0 being the lowest priority and priority 15 being highest). cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.5 advanced xbr traffic management 28236-DSH-001-B mindspeed technologies ? 2-17 figure 2-9 shows this prioritization as a global set of queues, but it is actually maintained on a per-transmit opportunity basis. in this way, high priority traffic is transmitted up to its gcra limits but does not block lower priority traffic when idle. the cn8236 asynchronously multiplexes traffic based on the above schemes as the tx fifo buffer empties. figure 2-9. multi-level model for prioritizing segmentation traffic (1) (1) (2) (2) (3) (3) (5) (5) (4) (4) host sar to phy data buffers transmit queues (32) segmentation coprocessor tx fifo buffer full/empty start next tx vcc id # traffic parameters conforming vcc id # ubr/vbr/abr vcc id # cbr xbr traffic manager vcc control tables schedule table abr templates 16 ubr/vbr/abr priority queues the user initializes traffic parameters on a per-vcc basis. user selects priority or round-robin service policy on transmit queues. the segmentation coprocessor notifies the traffic manager when a vcc becomes active, through reading new entries from the transmit queue. each conforming non-cbr vcc is assigned to a priority queue, while conforming cbr vccs are simply slated for transmit. the highest priority conforming cell is formatted and put on the tx fifo buffer for transmit. note(s): 8236_009 2.0 architecture overview cn8236 2.5 advanced xbr traffic management atm servicesar plus with xbr traffic management 2-18 mindspeed technologies ? 28236-DSH-001-B 2.5.1 cbr traffic the cbr service category requires guaranteed transmission rates, and constrained cdv. the cn8236 facilitates these needs when generating cbr traffic by pre-assigning specific schedule slots to cbr vccs. for each cbr-assigned cell slot, the cn8236 generates a cell for that specific vcc unless data is not available. the cn8236 also minimizes cdv by basing all traffic management on a local reference clock. the cn8236 provides a mechanism to exactly match the scheduled rate of a cbr channel to the rate of its data source. to accomplish this rate-matching, the host can occasionally instruct the xbr scheduler to skip one transmit opportunity on a channel. the cn8236 manages cbr tunnels in the same manner as a cbr vcc. however, instead of one vcc, several ubr, vbr, or abr vccs can be scheduled within this cbr tunnel, in round-robin order. unused cbr and tunnel time slots are automatically made available to vccs of other service categories by the xbr scheduler. 2.5.2 vbr traffic the cn8236 takes advantage of the asynchronous nature of atm by reserving bandwidth for vbr channels at average cell transmission rates without pre-assigning hardcoded schedule slots, as with cbr traffic. this dynamic scheduling allows vbr traffic to be statistically multiplexed onto the atm line, resulting in better utilization of the shared bandwidth resources. the xbr scheduler supports multiple priority levels for vbr traffic. through the combination of vbr parameters and priorities, it is possible to support real-time vbr services. the outgoing cell stream for each vbr vcc is scheduled according to the gcra algorithm. the gcra i and l parameters control the per-vcc peak cell rate (pcr) and cell delay variation tolerance (cdvt) of the outgoing cell stream on any channel. this guarantees compliance to policing algorithms applied at the network ingress point. the user can control the granularity of rate by dictating the number of schedule slots in the schedule table. channels can be rate-shaped as vcs or vps according to one of three vbr definitions. vbr1 controls pcr and cdvt. vbr2 controls pcr and cdvt, as well as sustained cell rate (scr) and burst tolerance (bt). vbrc (also called vbr3) controls pcr and cdvt on all cells, but controls scr on only clp = 0 (high priority) cells. cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.5 advanced xbr traffic management 28236-DSH-001-B mindspeed technologies ? 2-19 2.5.3 abr traffic the cn8236 implements the atm forum abr flow control algorithms. the cn8236 acts as a fully compliant abr source and destination, as defined in the tm 4.1 specification. the abr service category effectively allows low cell loss transmission through the atm network by regulating transmission based upon network feedback. the abr algorithms regulate the rate of each vcc independently. the cn8236 employs an internal feedback control loop mechanism to enable the tm 4.1 atm source specification. the sar utilizes the dynamic rate adjustment capability of the xbr scheduler as the atm source ? s variable traffic rate-shaper. the cn8236 injects an in-rate stream of forward rm cells for each abr vcc. when these cells return to the cn8236 ? s receive port as backward rm cells after a round trip through the network, the cn8236 processes these cells and uses the data returned as feedback to dynamically adjust the rates on each abr channel. the cn8236 also responds to an incoming abr cell stream as an abr destination. the reassembly coprocessor processes received forward rm cells. it turns around this incoming information to the segmentation coprocessor, which formats backward rm cells containing this information, and inserts these turnaround rm cells into the transmit cell stream. the exact performance of the rate-shaper is governed by one or more abr templates in sar-shared memory. each vcc is assigned to one of these templates. the templates control such behaviors as the size of the additive rate increase factors or multiplicative rate decrease steps. each vcc ? s rate varies across the template independently. 2.5.4 ubr traffic the ubr service category is intended for nonreal-time applications that do not require tightly constrained delay and delay variation, such as traditional computer communications applications like file transfer and e-mail. those vccs which have not been assigned to one of the other service categories covered previously are scheduled as ubr traffic. all ubr channels within a priority are scheduled on a round-robin basis. to limit the bandwidth that a ubr priority consumes, the system designer should use a cbr tunnel in that priority level. 2.5.5 gfr traffic guaranteed frame rate is a new service category defined by the atm forum to provide a mcr qos guarantee for aal5 cpcs-pdus not exceeding a specified frame length. a gfr service connection is treated as ubr with a guaranteed mcr. the cn8236 implements gfr by scheduling/shaping the connections using both the vbr1 scheduling procedure (for the mcr rate value) and a ubr priority queue, thereby providing fair sharing for all gfr connections to excess bandwidth. 2.0 architecture overview cn8236 2.5 advanced xbr traffic management atm servicesar plus with xbr traffic management 2-20 mindspeed technologies ? 28236-DSH-001-B 2.5.6 xbr cell scheduler the xbr scheduler slates traffic for transmission according to a dynamic schedule table maintained in sar-shared memory. the table contains a user-programmable number of schedule slots. the duration of a single slot is a user-programmable number of system clock cycles. the xbr scheduler sequences through this table in a circular fashion to schedule traffic. by configuring the number of slots in the table and the duration of each slot, the system designer chooses a range of available rates. a specific rate for any channel is determined by how many slots in the table to which that channel is assigned. schedule slots not reserved for cbr during table setup are used for the rest of the service categories. the xbr scheduler implements mindspeed ? s proprietary per-vcc rate-shaping algorithms. the predecessor to the cn8236, the bt8230 sar, proved the core algorithms. the cn8236 extends algorithms use to other service classes. the cn8236 xbr scheduler shapes all traffic classes, including cbr, single leaky bucket vbr, dual leaky bucket vbr, abr, and ubr. the host configures the dynamic schedule table during system initialization, defining the table size in number of schedule slots and the length of each schedule slot in clock cycles. after setup, the cn8236 dynamically manages the entire table. some key features of the xbr scheduler are as follows: 1. per-vcc rate control guarantees conformance to gcra upc/policing 2. dynamic reallocation of link bandwidth to active channels 3. dynamic, fair sharing of bandwidth on oversubscribed lines 4. multiple scheduling priorities 5. fine-grained rate control 6. rate based on a user-supplied reference clock dynamic management provides on-the-fly reallocation of link bandwidth without host intervention. the cn8236 fairly distributes the link bandwidth to channels based upon their qos parameters and assigned transmission priority. as covered previously, the cn8236 supports 16 priorities in addition to preallocated cbr time slots. the xbr scheduler facilitates advanced network traffic management topologies. the cn8236 rate shapes vcs or vps. additionally, cbr tunneling allows ubr, vbr and/or abr traffic management schemes to operate under a preallocated cbr limit. cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.5 advanced xbr traffic management 28236-DSH-001-B mindspeed technologies ? 2-21 2.5.7 abr flow control manager the abr flow control manager operates in conjunction with the xbr scheduler to control the rate of abr channels. the cn8236 implements the tm 4.1 specification in a template-controlled hardware state machine. mindspeed provides an initial set of templates which reside in sar-shared memory. the information within these templates define conformance abr behavioral responses to network and connection states. the cn8236 generates abr source traffic, including internally generated rm cells, according to the template instructions. the reassembly coprocessor and the flow control manager collaboratively act as a fully compliant abr destination terminal. these templates provide three significant benefits to the user: 1. since they control the flow control manager state machine, they can be optimized for specific applications. 2. the programmability of the templates insulates the hardware from changes in tm 4.1 specification. 3. mindspeed provides the initial templates, which can be customized by the user later, shortening developmen t t ime. 2.0 architecture overview cn8236 2.6 burst fifo buffers atm servicesar plus with xbr traffic management 2-22 mindspeed technologies ? 28236-DSH-001-B 2.6 burst fifo buffers to conserve local memory bandwidth, the cn8236 does not use its local sram as a buffer for incoming or outgoing data. instead, the cn8236 uses six dedicated internal fifo buffers data as follows: two dma master burst fifo buffers (read =16 words; write, 512 or 2 k words, programmable via config1 bit 1). two dma slave burst fifo buffers, (read = 8 words and write = 64 words). one fifo buffer between the phy interface and the segmentation coprocessor ( 1 to 9 cells) . see section 4.2.4 . one fifo buffer between the phy interface and the reassembly coprocessor (64 words). figure 2-10 illustrates the data fifo buffer. figure 2-10. data fifo buffers pci pci master pci slave phy interface 16 512 or 2 k 8 64 1 to 9 cells 64 dma master read burst fifo buffer dma slave read burst fifo buffer dma slave write command + data fifo buffer dma master write burst fifo buffer transmit phy interface fifo receive phy interface fifo segmentation controller reassembly controller 8236_097 cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.7 implementation of oam-pm protocols 28236-DSH-001-B mindspeed technologies ? 2-23 2.7 implementation of oam-pm protocols the cn8236 provides internal support for the detection and generation of oam traffic, including pm oam. the cn8236 supports the f4 and f5 oam flows according to i.610. it monitors up to 128 channels and generates in-rate pm-oam cells. the cn8236 includes a local processor interface, providing the capability of sar-shared memory segmentation and reassembly. the user can thus route oam traffic, including pm traffic, to and from this optional local processor, thereby off-loading atm network management from the host. to facilitate this, the cn8236 provides the option of user-defined global status queues for both segmentation and reassembly and a global buffer queue for reassembly, to which the user can assign sar-shared memory addresses. the cn8236 then processes oam traffic via the local processor, thereby isolating the host from these management functions and focusing host processing power on atm user data traffic. 2.8 standards-based i/o pci bus i/o the pci bus interface implements the full set of address, data, and control signals required to drive the pci bus as a master, and contains the logic required to support arbitration for the pci bus. this interface is pci version 2.1-compliant. the pci bus interface also includes an i 2 c interface module that allows the pci core to connect to a serial eeprom. this 128-byte eeprom is used to store specific pci configuration information, loaded into the pci configuration space at reset. this allows for several user-configurable features: user control of the size of the memory block for pci addresses enabling byte swapping of control words across the pci bus loading of subsystem id and subsystem vendor id atm phy i/o the cn8236 ? s atm phy interface communicates with and controls the atm link interface device, which carries out all the transmission convergence and phy media-dependent functions defined by the atm protocol. two modes of operation are provided: standard utopia and slave utopia. standard utopia mode conforms to both utopia level 1 and level 2 standards for atm layer devices. slave utopia mode reverses the control direction for use in place of a phy on switch fabrics. 2.0 architecture overview cn8236 2.8 standards-based i/o atm servicesar plus with xbr traffic management 2-24 mindspeed technologies ? 28236-DSH-001-B sar shared memory i/o to simplify system implementations, the cn8236 integrates a complete memory controller designed for direct interface to common static rams (srams). the cn8236 ? s memory controller operates at 33 mhz and can access up to 8 mb of sram memory. the memory controller also arbitrates access to the internal control and status registers by the host and local processors. the memory banks can be configured to a variable number of sizes. all of this affords a wide degree of flexibility in sar-shared memory architecture. local processor i/o the local processor interface in the cn8236 allows an optional external cpu to be directly connected to the device to serve as a local controlling intelligence that can handle initialization, connection management, overall data management, error recovery, and oam functions. the use of a local processor for these functions allows atm message data to flow to and from host system memory in a substantially larger bandwidth, because the local processor is handling the out-of-band functions described above. the processor interface is loosely coupled, meaning that the processor connects to the cn8236 through bidirectional transceivers and buffers for the address and data buses. this allows the processor fast access to cn8236 memory and registers, but insulates the cn8236 from processor instruction and data cache fills. it also allows the processor to control multiple cn8236s or phy devices if desired. boundary scan i/o and loopbacks the cn8236 includes five pins for joint test action group (jtag) boundary scan, for board-level testing. the cn8236 incorporates an internal loopback from the segmentation coprocessor to the reassembly coprocessor to facilitate system diagnostics. cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.9 electrical/mechanical 28236-DSH-001-B mindspeed technologies ? 2-25 2.9 electrical/mechanical the cn8236 is a cmos device packaged in a 388-pin ball grid array (bga) format. it operates from a 3.3 v power supply and within the standard industrial temperature range. the device inputs are tolerant of 5 v signal levels, so external 5 v devices can be used. any i/o (except pci) that requires a pullup must be tied through a resistor to 3.3 v and not 5 v. 2.10 logic diagram and pin descriptions a functionally partitioned logic diagram of the cn8236 is illustrated in figure 2-11 . pin descriptions, names, and input/output assignments are detailed in table 2-1 . 2.0 architecture overview cn8236 2.10 logic diagram and pin descriptions atm servicesar plus with xbr traffic management 2-26 mindspeed technologies ? 28236-DSH-001-B figure 2-11. cn8236 logic diagram (1 of 3) had31 hc/be3* hpar hframe* hirdy* htrdy* hstop* hdevsel* hidsel hgnt* hperr* hserr* hclk hrst* hreq* hint* pci interface signals i/o i/o i/o i/o i/o i/o i/o i/o i i i/o od i i o od address/data bus command/byte enable address/data command parity framing signal transactor initiator ready transaction target ready transaction termination bus device acknowledge bus device slot select bus grant bus parity error system error bus clock system reset arbiter bus request interrupt request host aalx interworking signals y26 aa25 l23 hled* od led power l4 henum* od enum# b23 w24 had30 had29 had28 had27 had26 had25 had24 had23 had22 had21 had20 had19 had18 had17 had16 had15 had14 had13 had12 w25 w26 v24 v25 v26 u23 u24 t25 r23 r24 r25 r26 p24 p25 p26 j26 j25 j24 h25 had11 had10 had9 had8 had7 had6 had5 had4 had3 had2 had1 had0 hc/be2* hc/be1* hc/be0* h24 h23 g26 g25 f25 f24 f23 e26 e23 d26 d25 d24 t23 n26 k23 f26 k24 m25 m24 m23 l25 l26 t24 y25 l24 n23 y23 pci5v hswitch* ab26 i bus signalling hfiford5 c23 hfiford4 a25 hfiford3 d23 hfiford2 c24 hfiford1 b26 hfiford0 c25 hfifowr5 f4 hfifowr4 e3 hfifowr3 d1 hfifowr2 d2 hfifowr1 d3 hfifowr0 c2 ii aalx fifo read strobes aalx fifo write strobes f3 i switch indicator 8236_098 cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.10 logic diagram and pin descriptions 28236-DSH-001-B mindspeed technologies ? 2-27 figure 2-11. cn8236 logic diagram (2 of 3) txd7 txsoc txclav txen* rxd15 rxpar rxsoc rxclav rxen* rxclk(frctrl) atm physical interface i/o i/o i/o i i i i/o i/o i o i/o transmit cell marker transmit flag transmit enable receive data receive data parity receive cell marker receive flag receive enable framer control/clock transmit data transmit address o transmit data parity i = input, o = output, od = open drain output framer configuration i frcfg1 the symbol (*) indicates active low frcfg0 af12 ae12 rxd14 rxd13 rxd12 rxd11 rxd10 rxd9 rxd8 utopia1 control txd6 txd5 txd4 txd3 txd2 txd1 txd0 af15 af16 ac14 ae5 af5 ac6 ad6 ae6 af6 ac7 ad7 ad5 ac10 ae11 ad10 ac13 txclk i transmit clock ad12 i ad14 af19 ac16 af17 ae17 ad17 ac17 ae18 ad18 ac18 ae19 af20 ae20 ad20 ac20 af21 ae21 ac21 af22 ae22 ad22 ac22 txpar ae16 txaddr4 txaddr3 txaddr2 txaddr1 txaddr0 txd15 txd14 txd13 txd12 txd11 txd10 txd9 txd8 rxd7 i/o receive address rxd6 rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 ac8 ad8 ae8 af8 ac9 af9 af2 ae3 af3 ad4 ae4 rxaddr4 rxaddr3 rxaddr2 rxaddr1 rxaddr0 framer configuration i paddr1 pbsel1 pbe3* pcs* (phycs1*) pas* pblast* (phycs2*) pwait* pwnr pfail* prdy* pdaen* local bus processor i i i i/o i/o i/o i i/o i o i/o word select bank select write byte-enables sar/atm chip select address strobe burst last local processor wait write not read self-test failed memory ready processor mode select i procmode interface paddr0 pbsel0 pbe2* pbe1* pbe0* b16 b10 c10 d11 a10 b12 c12 d12 c11 a15 d14 c14 a13 c13 c15 b13 b15 a16 d15 word select bank select i i prst* pint* od o data/address enable reset output interrupt output ae7 af7 8236_099 2.0 architecture overview cn8236 2.10 logic diagram and pin descriptions atm servicesar plus with xbr traffic management 2-28 mindspeed technologies ? 28236-DSH-001-B figure 2-11. cn8236 logic diagram (3 of 3) clk2x sysclk clkd3 trst* tclk tms tdi tdo boundary scan clocks/status i o o i i i i o system clock output divide by 3 clock output 2x clock input test logic reset test clock test mode select serial test data serial test data i = input, o = output, od = open drain output stat1 o sar status the symbol (*) indicates active low test signals stat0 o sar status sda scl serial eeprom o i/o n4 schref i scheduler reference clock ae1 ad25 ac23 ad26 ac25 ab24 ac24 ab23 m2 l2 f2 f1 eeprom data eeprom clock eepwr o d22 eeprom power 8236_100 ldata31 laddr18 mcs3* moe* mwe3* i/o i/o o o o memory data bus memory address bus memory bank chip selects memory read enable memory write enables mwr* write enable for by_16 ram o ram mode select i rammode laddr1 o memory address bus local bus memory interface n1 ldata30 p1 ldata29 p2 ldata28 p3 ldata27 r1 ldata26 r2 ldata25 r3 ldata24 r4 ldata23 t3 ldata22 t4 ldata21 u1 ldata20 u3 ldata19 u4 ldata18 v1 ldata17 v3 ldata16 v4 ldata15 w1 ldata14 w2 ldata13 w3 ldata12 y1 ldata11 y2 ldata10 y3 ldata9 y4 ldata8 aa1 ldata7 aa3 ldata6 aa4 ldata5 ab1 ldata4 ab2 ldata3 ab4 ldata2 ac1 ldata1 ac2 ldata0 ac3 laddr17 laddr16 laddr15 laddr14 laddr13 laddr12 laddr11 laddr10 laddr9 laddr8 laddr7 laddr6 laddr5 laddr4 laddr3 laddr2 b9 c9 d9 a8 b8 b7 c7 a7 d7 a6 b6 a5 b5 c5 d5 a4 b4 g4 mcs2* mcs1* mcs0* mwe2* mwe1* mwe0* laddr0 o memory address bus j2 j1 k4 k3 h1 g3 g2 h3 h2 j4 c4 a3 cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.10 logic diagram and pin descriptions 28236-DSH-001-B mindspeed technologies ? 2-29 table 2-1. hardware signal definitions (1 of 6) pin label signal name i/o definition host pci interface signals had[31:0] multiplexed address/data bus i/o used by the pci host or cn8236 to transfer addresses or data over the pci bus. hc/be[3:0]* command/byte enable i/o outputs a command (during pci address phases) or byte enables (during data phases) for each bus transaction. hpar address/data command parity i/o supplies the even parity computed over the had[31:0] and hc/be[3:0]* lines during valid data phases. it is sampled (when the cn8236 is acting as a target) or driven (when the cn8236 acts as an initiator) one clock edge after the respective data phase. hframe* framing signal i/o a high-to-low hframe* transition indicates that a new transaction is beginning (with an address phase). a low-to-high transition indicates that the next valid data phase ends the current transaction. hirdy* transaction initiator ready i/o used by the transaction initiator or bus master (either the cn8236 or the pci host) to indicate ready for data transfer. a valid data transfer occurs when both hirdy* and htrdy* are active on the same clock edge. htrdy* transaction target ready i/o used by the transaction target or bus slave (either the cn8236 or the pci bus memory) to indicate that it is ready for a data transfer. a valid data transfer occurs when both hirdy* and htrdy* are active on the same clock edge. hstop* transaction termination i/o driven by the current target or slave (either the cn8236 or the pci bus memory) to abort, disconnect, or retry the current transfer. the hstop* line is used by the pci master in conjunction with the htrdy* and hdevsel* lines to determine the type of transaction termination. hdevsel* bus device acknowledge i/o driven by a target to indicate to the initiator that the address placed on the had[31:0] lines (together with the command on the hc/be[3:0]* lines) has been decoded and accepted as a valid reference to the target ? s address space. once asserted, it is held by the cn8236 (when acting as a slave) until hframe* is deasserted; otherwise, it indicates (in conjunction with hstop* and htrdy*) a target abort. hidsel bus device slot select i signals the cn8236 that it is being selected for a configuration space access. hreq* arbiter bus request o asserted by the cn8236 to request control of the pci bus. hgnt* bus grant i asserted to indicate to the cn8236 that it has been granted control of the pci bus, and can begin driving the address/data and control lines after the current transaction has ended (indicated by hframe*, hirdy*, and htrdy*; all deasserted simultaneously). hint* interrupt request od signals an interrupt request to the pci host, and is tied to the inta_ line on the pci bus. 2.0 architecture overview cn8236 2.10 logic diagram and pin descriptions atm servicesar plus with xbr traffic management 2-30 mindspeed technologies ? 28236-DSH-001-B host pci interface signals hperr* bus parity error i/o driven asserted by the cn8236 (as a bus slave) or by a target addressed by the cn8236 when it acts as a bus master to indicate a parity error on the had[31:0] and hc/be[3:0]* lines. it is asserted when the cn8236 is a bus slave or sampled when the cn8236 is a bus master on the second clock edge after a valid data phase. the cn8236 drives the hperr* line only when acting as a slave. hserr* system error od indicates a system error or a parity error on the had[31:0] and hc/be[3:0]* lines during an address phase. this pin is handled in the same way as hperr*, and is only driven by the cn8236 when it acts as a bus slave. hclk bus clock i supplies the pci bus clock signal. hrst* system reset i performs a hardware reset of the cn8236 and associated peripherals when asserted. must be asserted for 16 cycles of hclk. pci5v bus signalling i must be tied high. this pad has an internal pullup resister to vdd. hswitch* switch indicator i logic low means switch locked, logic high means switch unlocked. signal pulled up internally. compact pci hot swap signal. hled* led power od 12 ma open drain. logic low turns on led. compact pci hot swap signal. henum* enum# od 8 ma open drain. compact pci hot swap signal. aalx hfiford[5:0] aalx fifo read strobes i aalx ingress fifo buffer read strobe. this signal is edge- detected inside the sar so no setup/hold time required. signals pulled up internally. hfifowr[5:0] aalx fifo write strobes i aalx egress fifo buffer write strobe. this signal is edge- detected inside the sar so no setup/hold time required. signals pulled up internally. atm phy interface frcfg[1:0] framer configuration i configuration pins frcfg[1,0] determine what framer interface the cn8236 supports. 00 = reserved; do not use 01 = utopia interface 10 = slave utopia interface 11 = reserved; do not use txdata[15:0] transmit data o carries outgoing data bytes to the framer chip in all framer modes (8 ma drive). txaddr[4:0] transmit address i/o utopia transmit address (8 ma drive). txpar transmit data parity o outputs the 8-bit odd parity computed over the txdata[15:0] lines in all framer modes (8 ma drive). txsoc transmit cell marker i/o in both utopia and slave utopia modes, the txsoc line is asserted by the cn8236 when the starting byte of a 53-byte cell is being output. (aka txmark ) table 2-1. hardware signal definitions (2 of 6) pin label signal name i/o definition cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.10 logic diagram and pin descriptions 28236-DSH-001-B mindspeed technologies ? 2-31 atm phy interface txclav transmit flag i/o in utopia mode, txclav indicates that the transmit buffer in the downstream link interface chip is full and no more data can be accepted. in slave utopia mode, this pin indicates to the link interface chip that the cn8236 transmit buffer is empty. (has pulldown resistor to pull inactive in master mode when not driven externally.) (aka txflag* ) (8 ma drive) txen* transmit enable i/o indicates that valid data has been placed on the txdata[15:0], txpar, and txsoc lines in the current clock cycle when the cn8236 is in utopia or slave utopia mode. this pin is an output in utopia mode and an input in slave utopia mode. (8 ma drive. has pullup resistor to pull inactive in slave mode when not driven externally.) txclk transmit clock i utopia transmit clock. has an internal pullup to v dd (cmos level). rxaddr[4:0] receive address i/o utopia receive address (8 ma drive). rxdata[15:0] receive data i transfers incoming data bytes from the link interface or framer chip to the cn8236 in all framer modes. rxpar receive data parity i should be driven with the 8-bit odd parity computed over the rxdata[7:0] lines by the link interface or framer chip in all framer modes. rxsoc receive cell marker i indicates that the current byte being transferred on the rxdata[7:0] lines is the starting byte of a 53-byte cell. has internal pulldown resistor. (aka rxmark) rxclav receive flag i/o in utopia mode, rxclav indicates that the receive buffer in the downstream link interface chip is empty, no more data can be transferred, and the rxdata[7:0], rxpar, and rxsoc lines are invalid. in slave utopia mode, this pin indicates to the framer chip that the receive fifo buffer in the cn8236 is full. 8 ma drive. has pulldown resistor to pull inactive in master mode when not driven externally. (aka rxflag* ) rxen* receive enable i/o in utopia mode, rxen* indicates that the cn8236 is ready to receive data on the rxdata[15:0],rxpar, and rxsoc lines in the next clock cycle. this pin is an output in utopia mode and an input in slave utopia mode. has pullup resistor to pull inactive in slave mode when not driven externally. 8 ma drive. rxclk framer control/clock i in utopia and slave utopia mode, the rxclk line should be driven with a clock that is synchronous to that used by the framer device for interfacing to the cn8236. the txdata[15:0], txpar, txsoc, txclav, txen*, rxdata[15:0],rxpar, rxsoc, rxclav, and rxen* lines must be synchronous to this clock in utopia mode, and maintain the specified setup and hold times with reference to its rising edge. when multi_clk is set to a 1 in the config1 register, the tx side of the utopia interface is synchronized to the txclk. table 2-1. hardware signal definitions (3 of 6) pin label signal name i/o definition 2.0 architecture overview cn8236 2.10 logic diagram and pin descriptions atm servicesar plus with xbr traffic management 2-32 mindspeed technologies ? 28236-DSH-001-B utopia1 utopia mode select i selects level 1/level 2 operation. in level 1 mode, address pins are forced to be outputs independent of master/slave mode. this input has a pullup resistor so the default is utopia level 1 mode. when utopia1 input is a logic high, the utopia address signals, txaddr[4:0] and rxaddr[4:0], are forced as outputs. local bus processor interface procmode processor mode select i when grounded, this input selects the local processor mode. when pulled to a logic high, the standalone mode is selected. paddr[1:0] word select inputs i the paddr[1,0] inputs are connected to the word select field of the cpu address bus (address bits [3, 2] for the intel i80960ca processor, which can perform 4-word burst transactions). these inputs are used by the cn8236 to allow single-cycle bursts to be performed without requiring very short memory access times. pbsel[1:0] bank select inputs i select one of four banks of memory to be accessed. they are decoded by the memory controller to generate the appropriate chip/bank selects to the external memory. pbe[3:0]* write byte-enables i supplies byte enables for each local processor memory access. these pins are only relevant during writes by the local processor to sar-shared memory. each byte enable line corresponds to a specific byte lane in the ldata[31:0] data bus: pbe[0]* corresponds to ldata[7:0], pbe[1]* to ldata[15:8], pbe[2]* to ldata[23:16], and pbe[3]* to ldata[31:24]. pcs* (phycs1*) sar chip select atm phy chip select (in standalone mode) i/o in local processor mode with procmode tied low, pcs* is the sar chip select input. in standalone mode, this pin is phycs1*, which can be connected to the chip select input of the mindspeed phy device. pas* address strobe i/o indicates a local processor address cycle. in standalone mode, pas* is used to drive the as* pin of the mindspeed phy device. pwnr write/not read i/o the pwnr input indicates the direction of a local processor transfer. a logic 1 indicates a write; a logic 0 indicates a read. during standalone mode, this output provides the same function for the mindspeed phy device. pwait* processor wait i used by the local processor or external logic to insert wait states for read or write transactions. pblast* (phycs2*) burst last atm phy chip select (in standalone mode) i/o in local processor mode, this input is used by the processor to indicate the end of a transaction. during standalone mode, this output is a second chip select, phycs2*. prdy* memory ready o signals that the memory or control register has accepted the data on a write, or that data is available to latch by the local processor on a read cycle. table 2-1. hardware signal definitions (4 of 6) pin label signal name i/o definition cn8236 2.0 architecture overview atm servicesar plus with xbr traffic management 2.10 logic diagram and pin descriptions 28236-DSH-001-B mindspeed technologies ? 2-33 local bus processor interface pdaen* data/address enable i/o connected to the output enable input of the bidirectional transceivers and buffers used to isolate the cn8236 data and address bus from the local processor. in standalone mode, this input is connected to the phy device ? s interrupt output(s). pfail* self-test failed i the local processor can indicate a failure of its internal self-test or initialization processes by asserting the pfail* input to the cn8236. pint* interrupt output od asserted by the cn8236 to the local processor to signal an interrupt request in local processor mode. prst* reset output o asserted by the cn8236 to the local processor whenever the hrst* input is asserted, or when the lp_enable bit in the config0 register is a logic low. local bus memory interface ldata[31:0] memory data bus i/o data i/o bus. used for memory reads and writes, and control and status register access by the local processor. laddr[18:2] memory address bus i/o address i/o bus. used for memory reads and writes, and control and status register access by the local processor. laddr[1:0] memory address bus o the two least significant bits of address i/o bus. used for memory reads and writes, and control and status register access by the local processor. mcs[3:0]* memory bank chip selects o selects one of four addressable banks of sram memory. moe* memory read enable o indicates that a read cycle is proceeding and the memory device output buffers should be enabled, driving data onto the ldata[31:0] lines. mwe[3:0]* memory byte write enables o memory byte write enables for by_4 or by_8 srams. for by_16 devices, these outputs are byte enables that are active on writes and reads. mwr* write enable o memory write enable for by_16 srams. rammode ram mode select i selects ram chips supported. 1 = by_16 memory devices 0 = by_4 or by_8 memory devices clocks/status clk2x 2x clock input i double frequency (from sysclk) cmos level input (66 mhz maximum). sysclk system clock output o this divide by 2 of clk2x is the internal system clock and the external system clock (33 mhz maximum). clkd3 divide by 3 clock output o this output clock is a 50% duty cycle, one-third divide of clk2x; it can be used for the utopia interface clock (22 mhz maximum). stat[1,0] sar status o cn8236 internal status outputs. internal status controlled by the stat_mode[4:0] field in the config0 register. schref scheduler reference clock i external scheduler reference clock. table 2-1. hardware signal definitions (5 of 6) pin label signal name i/o definition 2.0 architecture overview cn8236 2.10 logic diagram and pin descriptions atm servicesar plus with xbr traffic management 2-34 mindspeed technologies ? 28236-DSH-001-B boundary scan test signals trst* test logic reset i when a logic low, this signal asynchronously resets the boundary scan test circuitry and puts the test controller into the reset state. this state allows normal system operation. tie to ground when boundary scan is not implemented. this pad has an internal pullup resister to vdd. tclk test clock i generated externally by the system board or by the tester. tie to ground when boundary scan is not implemented. tms test mode select i decoded to control test operations. this pad has an internal pullup resister to vdd. tdo serial test data o outputs serial test pattern data. tdi serial test data i input for serial test pattern data. this pad has an internal pullup resister to vdd. serial eeprom sda eeprom data i/o serial i 2 c data. scl eeprom clock o serial i 2 c clock. eepwr eeprom power o 12 ma drive. direct buffer of hrst* input. supply voltage vdd power ? forty-nine balls are provided for supply voltage. vss ground ? eighty-five balls are provided for ground. (the 36 balls in the center help in heat dissipation.) vgg esd protection ? voltage clamp i provides electrostatic discharge (esd) protection and over voltage protection. when the device is used with 5 v devices on the board, tie this pin to 5 v for 5 v signal tolerance. otherwise, tie to 3.3 v. note: the 5 v supply must be applied concurrent to the 3.3 v supply. table 2-1. hardware signal definitions (6 of 6) pin label signal name i/o definition 28236-DSH-001-B mindspeed technologies ? 3-1 3 3.0 host interface 3.1 overview the cn8236 segments and reassembles user data packets at 200 mbps simplex, and over 155 mbps full duplex. the actual segmentation and reassembly processes execute without run-time host control. however, the atm host system supplies the data for transmission and buffers for received data. in addition to this control, the host processes status returned from the sar. to take advantage of the cn8236 ? s high throughput, the host must process control and status information at a comparable rate. in cases such as the example above, the service rate places extraordinary performance requirements on the host system. high throughput systems require large numbers of processing cycles and efficient use of system buses. the cn8236 provides a flexible, high-performance, host interface architecture. with this interface, the cn8236 facilitates a scalable, distributed host system. the interface also minimizes the impact of an atm port on the host system ? s pci bus. application example an ethernet switch uses a cn8236-based subsystem as an uplink to an oc-3 atm backbone. under worst case conditions, ethernet packets (64 octets) map into two atm cells. at oc-3 rates, the cn8236 converts 176.6 k packets/second (kpps) to cells in each direction. therefore, the host must process control and status information for a total of 353.2 kpps. this packet rate equates to a packet service time of 2.83 s/packet. 3.0 host interface cn8236 3.2 multiple client architecture atm servicesar plus with xbr traffic management 3-2 mindspeed technologies ? 28236-DSH-001-B 3.2 multiple client architecture the cn8236 provides multiple independent control and status communication paths. each communication path, or flow, consists of a control queue and a status queue for both segmentation and reassembly. the host assigns each of these independent flows to system clients, or peers. as throughput requirements escalate, the host system can add processing power in the form of additional peers. this degree of freedom creates a scalable host environment. the cn8236 provides an atm server for up to 32 clients. figure 3-1 illustrates this client/server relationship. 3.2.1 logical clients as shown in figure 3-1 , the clients do not need to be physically distinct pci peers. the host can also assign control and status queues to system software tasks, or logical clients. since the queues offer individually distinct communication paths, each logical client interfaces to the cn8236 independently. due to its server architecture, the cn8236 supplies the synchronization between asynchronous tasks requiring atm services. figure 3-1. client/server model of the cn8236 pci cards pci motherboard logical client logical client at m user-network interface atm server pci interface (up to 32 clients) cn8236 subsystem host data path host control/status flow legend: physical client physical client 8236_010 cn8236 3.0 host interface atm servicesar plus with xbr traffic management 3.2 multiple client architecture 28236-DSH-001-B mindspeed technologies ? 3-3 3.2.2 resource allocation with either phy pci peers, logical peers, or some combination of the two types, the cn8236 multiplexes each peer ? s transmitted packets onto the line and routes incoming packets to the appropriate peer. the host system allocates shared resources, such as host and sar-shared memory, vpi/vci address space, and cbr time slots, to peers and clients arbitrarily. 3.2.3 resource isolation because each peer is assigned to an independent control and status path, the cn8236 isolates the resources of each peer. this simplifies resource management. in addition, queue error conditions caused by a single peer do not affect any other peers. 3.2.4 peer-to-peer transfers the multiple queue architecture of the cn8236 also enables peer-to-peer pci transfers. the cn8236 transfers atm cells as a pci master. since the buffer control structures are independent for each peer, each identifies a unique address range in pci memory space. the host defines the address range of each peer. the cn8236 transfers data within this address range. an address range corresponds either to a region of centralized host memory, or to a set of peer resident buffers. figure 3-2 shows the difference between these two options. centralized memory buffers require store-forward operations, while the peer buffers enable peer-to-peer transfers. thus, peer-to-peer transfers reduce the use of the pci bus. application example a system designer implements a cn8236 terminal as an atm uplink for a service access multiplexer (sam). the sam is comprised of the atm card and several frame relay adapter cards. the host assigns each frame relay adapter card to a set of cn8236 control and status queues at initialization. during operation, one of the frame relay adapter cards experiences a hardware failure. the failure prevents the card?s processor from servicing the cn8236?s reassembly status queue. eventually, the cn8236 fills the queue and is unable to proceed?this situation is referred to a queue overflow. the cn8236 shuts down reassembly on vccs that are assigned to the overflowed queue only. since the other cards in the system are assigned to other status queues, their vccs remain unaffected by the failure. 3.0 host interface cn8236 3.2 multiple client architecture atm servicesar plus with xbr traffic management 3-4 mindspeed technologies ? 28236-DSH-001-B 3.2.5 local processor clients the cn8236 supports limited bandwidth sar-shared memory segmentation and reassembly. any peer can use the local processor port instead of the pci bus for data traffic, control, and status. hosts can use sar-shared memory for control and status, but transfer data across the pci bus. this out-of-band. control configuration diverts control overhead from the pci bus, lessening the burden of at m ? s high throughput and robust management requirements on the host system. figure 3-3 shows an out-of-band control architecture. figure 3-2. peer-to-peer vs. centralized memory data transfers pci peer frame i/o pci host frame i/o peer memory centralized memory pci motherboard pci card pci bus cn8236 1 # 1 2 # a t m n e t w o r k legend: pci transaction peer-to-peer transaction centralized memory transaction data buffer 8236_011 figure 3-3. out-of-band control architecture at m network host system cn8236 subsystem pci bus local processor port legend: data flow host control/status flow 8236_012 cn8236 3.0 host interface atm servicesar plus with xbr traffic management 3.3 write-only control and status 28236-DSH-001-B mindspeed technologies ? 3-5 3.3 write-only control and status for host-based applications, the host manages the cn8236 sar using write-only control and status queues. this architecture minimizes pci bus use by eliminating reads from the control path. pci writes use the bus much more efficiently than pci reads. during a pci write, the target can post the write data in an internal fifo buffer, terminate the transaction, and immediately release the bus. on the other hand, during reads, the target retrieves the data while holding the bus. since the data retrieval takes some time, reads increase the pci bus utilization. the cn8236 ? s write-only architecture uses reads only for segmentation data (pdu) fetches. all control and status transactions are writes. this section describes the management of write-only queues. the purpose and entries of each class of queue are described in later chapters. table 3-1 defines the cn8236 control and status queues. 3.3.1 write-only control queues the host controls run-time segmentation and reassembly through write-only control queues. there are two types of control queues ? the segmentation transmit queues and the reassembly free buffer queues. the host submits buffers of pdu data for segmentation on the transmit queues and supplies empty buffers for received data on the free buffer queues. each type of queue is managed as a write-only control queue. these queues reside in sar-shared memory at a location defined by a base register pointer. to allow multiple clients, the cn8236 supports 32 queues of each type. the sar and host manage each queue independently, through queue management variables. the sar stores its variables in internal registers called base tables. the host maintains its own variables within its driver. each queue contains a programmable number of queue entries. table 3-1. cn8236 control and status queues type segmentation reassembly control transmit queue free buffer queue status segmentation status queue reassembly status queue 3.0 host interface cn8236 3.3 write-only control and status atm servicesar plus with xbr traffic management 3-6 mindspeed technologies ? 28236-DSH-001-B 3.3.1.1 control variables table 3-2 describes the variables for write-only control queues. 3.3.1.2 queue management figure 3-4 illustrates the control queue management algorithm. the host initializes all of the variables described in table 3-2 . once the sar is enabled, it maintains the read pointer. when the sar processes a queue entry, it advances the read pointer (read++). since the queues are circular, the pointer eventually wraps back to 0. it also advances an internal counter, update (update++). when interval queue entries have been processed, the sar writes its current position in the queue, read, to a host variable, read_ud. the host determines the magnitude of interval at initialization. larger numbers result in fewer overhead pci accesses, but also introduces larger latency between host updates, which reduces the effective size of the queue. table 3-2. write-only control queue variables variable definition location initialization write current host position in queue host variable 0 read_ud last known sar position in queue as seen by host host word aligned variable 0 read current sar position in queue sar base table 0 interval number of queue entries processed by sar before writing read_ud sar register host defined update number of queue entries since last write of read_ud sar base table 0 read_ud_pntr sar pointer to read_ud sar base table &read_ud cn8236 3.0 host interface atm servicesar plus with xbr traffic management 3.3 write-only control and status 28236-DSH-001-B mindspeed technologies ? 3-7 the host also maintains a pointer into the queue, write. when the host submits a new entry, it must first ensure that the sar has already processed the entry location. the host compares write to read_ud. if (write+1) modulo size_of_queue equals read_ud, the host halts writing to the queue. this results in being able to use only n-1 queue entries. however, if this is not done, then a full condition cannot be distinguished from an empty condition. the host must wait until read_ud is modified by the sar before proceeding. this algorithm ensures that the host does not overflow the control queue, without reading the queue itself. once it has verified its ownership of the entry, the host writes the entry and increments its write pointer (write++). during this write, the host sets the valid bit (vld) in the entry to 1. the cn8236 snoops the writes to the control queue areas. once a write is detected to a specific queue, the sar attempts to process the queue entry at read. before acting on the entry, the sar checks for ownership of the entry, indicated by the vld bit. once the cn8236 has processed the entry, it resets the vld bit to 0. 3.3.1.3 underflow conditions an underflow condition occurs when the sar attempts to retrieve a queue entry and the host has not yet supplied this entry. this condition happens only on the free buffer queues. the sar detects this condition by checking the queue entry vld bit. once detected, the sar enters an underflow detected state on this queue only. since this signifies that no data buffers are available for reassembly, the sar initiates epd on all channels assigned to this queue. chapter 5.0 describes sar handling of free buffer queue underflow in detail. figure 3-4. write-only control queue 00000000 11111111 1 1 111111111 1 0000 read_ud write++ read_ud_pntr (base table) pci bus boundary vld bit update= interval n y update++ (base table) read++ base register update host update=0 read_ud_pntr= read 8236_101 3.0 host interface cn8236 3.3 write-only control and status atm servicesar plus with xbr traffic management 3-8 mindspeed technologies ? 28236-DSH-001-B 3.3.2 write-only status queues the sar reports status to the host through write-only status queues. both the segmentation and reassembly coprocessors use their own format of status queue. however, the cn8236 manages all status queues with the same algorithm. these queues reside in host memory, or optionally sar-shared memory, at a location defined within the base table for each queue. the host must assign word-aligned (4-byte) status queue base addresses. to support multiple clients, the cn8236 provides 32 queues of each type. the sar and host manage each queue independently through queue management variables. the sar stores its variables in internal base table registers. the host maintains its variables in its driver. each queue contains a programmable number of queue entries. 3.3.2.1 control variables table 3-3 describes the variables for write-only status queue management. 3.3.2.2 queue management figure 3-5 illustrates the status queue management algorithm. the host initializes all of the variables described in table 3-3 . the sar maintains its own write pointer, write. the cn8236 reports status to the host by writing a status queue entry. after it writes the entry, the cn8236 increments its write pointer (write++). this write also triggers a maskable interrupt. the host either responds to this interrupt, or periodically polls the status queue. the vld bit in each queue entry enables polling. the sar sets the vld bit equal to 1 when it writes a status queue entry. the host resets it to 0 after processing an entry. table 3-3. write-only status queue variables variable definition location initialization write current sar position in queue sar base table 0 read_ud last known host position in queue as seen by sar sar base table 0 read current host position in queue host variable 0 interval number of queue entries processed by host before writing read_ud host variable host defined update number of queue entries since last write of read_ud host variable 0 read_ud_pntr host pointer to read_ud host variable &read_ud cn8236 3.0 host interface atm servicesar plus with xbr traffic management 3.3 write-only control and status 28236-DSH-001-B mindspeed technologies ? 3-9 the host also maintains a pointer (read) into the status queue. each time it services an entry, it increments a counter (update++). when this counter reaches a host-specified threshold (interval), the host informs the sar of its current queue position by writing read_ud in the queue ? s base table register. 3.3.2.3 overflow conditions an overflow condition occurs when the sar attempts to write a status queue entry, but the status queue entry is unavailable. this condition can happen for both the segmentation and reassembly status queues. chapter 4.0 and chapter 5.0 describe the handling of this event. in either case, the result is severe and therefore undesirable. the host control service rate of the status queue should match or exceed the status queue reporting rate of the cn8236. the cn8236 detects an overflow condition by comparing its current write pointer to the read_ud pointer, that is, the last known host read position. if write points to the entry immediately before the read_ud (write = read_ud -1), the sar detects the imminent overflow condition. to inform the host of the event, the sar sets the overflow indication bit (ovfl) in the exhausted status queue. since it cannot report status, the cn8236 segmentation and reassembly processing is temporarily halted for vccs assigned to the overflowed status queue only. all other processes and queues remain operational. figure 3-5. write-only status queue 00000000 11111111 1 1 111111111 1 0000 read_ud (base table) write++ (base table) pci bus boundary vld bit update= interval n n y y update++ signal overflow read++ base_pntr (base table) update sar update=0 read_ud_pntr= read write = read_ud - 1 read_ud_pntr 8236_102 3.0 host interface cn8236 3.3 write-only control and status atm servicesar plus with xbr traffic management 3-10 mindspeed technologies ? 28236-DSH-001-B 3.3.2.4 status queue interrupt delay status queue interrupt delay has been added in order to reduce the interrupt processing load on the host. this is valuable in a network interface card (nic)-based solution, where the sar resides in an environment in which the host is not dedicated to datacom processing. both a timer hold-off mechanism and an event counter mechanism are implemented and work in parallel. the timer hold-off mechanism uses the alarm1 and clock register resources to implement an interval timer. interrupts due to status queue writes, either host or local, are delayed until the timer expires. the event counter mechanism delays the assertion of the interrupt due to status queue writes until a fixed number of status queue writes have occurred. both mechanisms work in parallel (not in series) if enabled, so that either mechanism needs to expire before the interrupt propagates to the output pin. interrupts due to conditions other than status queue writes are not delayed. timer hold-off mechanism the timer hold-off mechanism is enabled by setting int_delay (en_timer) to a logic high. the alarm1 register is set to a value that holds off the interrupt for a specified period of time. the user initializes the clock register to 0. when the value in the clock register is greater than the value in the alarm1 register, status queue interrupts are allowed to propagate to the appropriate interrupt pins, hint* or pint*. the clock register is set to 0 once an interrupt has propagated to the output pin, thus closing the status queue write interrupt window. the timer mechanism cannot be used in both the pint* and hint* circuits at the same time. the timer mechanism is configured via the int_delay (timer_loc) bit. event counter mechanism the event counter mechanism is enabled by setting int_delay (en_stat_cnt) to a logic high. an internal counter is implemented that counts the number of status queue write events. the number of events before opening the interrupt window is programmable via the int_delay(stat_cnt) field. the window is closed for stat_cnt number of events. when the internal counter has reached the value of stat_cnt, the interrupt window is opened, which allows the interrupt to propagate to the output pin. the counter is reset when the status registers are read and the interrupt output goes inactive. 28236-DSH-001-B mindspeed technologies ? 4-1 4 4.0 segmentation coprocessor 4.1 overview at m ? s cell transport mechanism enables large numbers of virtual channels or vccs to be multiplexed onto a single phy interface. the segmentation process converts user data (typically ethernet, token ring, or frame relay packets) into atm cells. the cn8236 can segment 64 k vccs simultaneously. the segmentation coprocessor block independently segments each channel and multiplexes the vccs onto the line with cell level interleaving. the cn8236 xbr traffic manager determines the order of execution of these independent processes to ensure the requested qos for every channel. for each cell transmission opportunity, the xbr traffic manager tells the segmentation coprocessor which vcc to send. therefore, the segmentation coprocessor acts as a slave to the xbr traffic manager. in addition to converting blocked user data into atm cells, the cn8236 generates all aal overhead for aal3/4 and aal5, or optionally uses a null adaptation layer, aal0. the cn8236 also generates the atm cell header, as defined by the host, for each vcc. furthermore, the segmentation coprocessor and xbr traffic manager together provide service-specific features to enhance the performance of frame relay internetworking and lan emulation. 4.0 segmentation coprocessor cn8236 4.2 segmentation functional description atm servicesar plus with xbr traffic management 4-2 mindspeed technologies ? 28236-DSH-001-B 4.2 segmentation functional description 4.2.1 segmentation vccs a vcc specifies a single vc or vp in the atm network. the cn8236 supports up to 64 k segmentation vccs, referenced by a unique index, vcc_index. the vcc_index identifies a location in the segmentation vcc table, an array of 10-word segmentation vcc channel descriptors. except for abr service category vccs, each segmentation vcc occupies a single descriptor in the table (10 words). due to the large number of specified parameters for abr traffic, abr vccs occupy two descriptors (20 words) in the segmentation vcc table. the vcc_index for abr vccs points to the first of the two descriptors, and must be evenly divisible by two. a segmentation vcc table channel descriptor consists of two parts: an aal specific vcc table entry (seven words) and a service class specific schedule state (sch_state). for non-abr vccs, the remaining three words of the channel descriptor form the sch_state entry. for an abr vcc, the sch_state entry contains 13 words, which require an additional descriptor location. 4.2.1.1 segmentation vcc table figure 4-1 shows a vcc table with a cbr vcc at vcc_index 3, an abr vcc located at vcc_index 0x1000, and a non-abr vcc at vcc_index 0xfffd. the host allocates the vcc table in sar-shared memory and provides an address to the sar in a base register field, seg_vbase(seg_vccb). for the most efficient abr performance, all abr vccs should be placed in the upper half of the vcc table (that is, with smaller vcc indexes). the only reason not to put abr vccs at the lowest address range is to place cbr vccs in the first 32 k vcc addresses. valid vcc indexes for cbr traffic range from 0x0000 to 0x7ffe, due to the limit imposed by a 15-bit address. a vcc index of 0xffff for non-cbr and 0x7fff for cbr indicates a null vcc. while the cn8236 accepts any vcc index within the range of 64 k vcc indexes, the actual number of segmentation vccs allowed by the sar is limited by the amount of sar-shared memory available in which to allocate and create segmentation vcc tables, transmit queues, etc. cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.2 segmentation functional description 28236-DSH-001-B mindspeed technologies ? 4-3 the vcc table entry contains generic information common to all traffic classes. this includes a default atm header, which the host can modify during the segmentation process. see section 4.3.1 , for full details of the structure of a segmentation vcc table entry. 4.2.1.2 vcc identification the host allocates a region of sar-shared memory for the segmentation vcc table at system initialization, based on the maximum number of connections and the maximum number of abr connections. the host informs the sar of the location of the table through the internal base register, seg_vbase (seg_vccb). once a table has been established, the host assigns segmentation vccs to entries in the table. the host describes the seg vcc by initializing the seg vcc table entry including the sch_state portions of the assigned vcc. the vcc_index, defined as the offset into the table in 10-word increments, uniquely identifies a segmentation channel. in all communication between the sar and the host, a vcc_index field specifies a vcc. figure 4-1. segmentation vcc table sch_state sch_state base register (seg_vbase(seg_vccb)<<5) vcc_index = 0x3 (cbr vcc) vcc_index = 0x1000 (abr vcc) vcc_index = 0xfffd (non-abr vcc) vcc_index = 0x0 vcc table 10 words = 1 descriptor 7 words 3 words 1 descriptor 7 words 13 words 2 descriptors vcc table entry sch_state } } } } } } } vcc table entry vcc table entry 8236_095 4.0 segmentation coprocessor cn8236 4.2 segmentation functional description atm servicesar plus with xbr traffic management 4-4 mindspeed technologies ? 28236-DSH-001-B 4.2.2 submitting segmentation data once the host establishes a connection, it supplies data for segmentation. the host submits full or partial pdus, either one at a time or in batches, for individual vccs. the sar accepts pdus at any time, regardless of the state of the connection, and segments data on each vcc independently. 4.2.2.1 user data format the cn8236 accepts user pdus as sequences of data buffers. sar-shared memory resident segmentation buffer descriptors (sbds) provide the address, length and control information for buffers. the host forms pdu buffer sequences by linking buffer descriptors. the data buffers themselves contain only user data and reside in host (or optionally sar-shared) memory. host data buffers contain the bulk of segmentation data, and can begin on any byte-aligned address in the sar ? s pci address space. note: sar-shared memory data buffer segmentation should be limited to low bandwidth applications, such as signalling, oam, and ilmi. 4.2.2.2 buffer descriptors the host submits data using the following process sequence. first, the host allocates an sbd for each buffer in a message. sbds reside in sar-shared memory, and must begin on word-aligned addresses. then, the host describes the buffers in the sbd. this description includes the address and length of the buffer, as well as control fields for the sar during buffer segmentation. these control fields specify the vcc_index, the aal type, and header override information for the buffer. the host then creates pdu message sequences by concatenating buffers. the host forms the buffer sequence by linking a list of buffer descriptors using the sbd ? s next field. two bits in the sbd control fields delineate the beginning and end of messages. one bit, bom, specifies that the buffer contains the beginning of a message. the second bit, eom, notifies the sar that the buffer contains the end of the current message. the host identifies the end of the sbd chain by terminating the list with a null (0) next pointer. table 4-1 describes how to use these bits. table 4-1. segmentation pdu delineation bom eom buffer to message adaptation 0 0 segment as continuation of message (com). 0 1 terminate current cpcs-pdu at end of buffer (eom). 1 0 restart cpcs-pdu generation (bom). wait for eom for termination. 1 1 buffer contains complete message. restart/terminate cpcs-pdu. cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.2 segmentation functional description 28236-DSH-001-B mindspeed technologies ? 4-5 4.2.2.3 host linked segmentation buffer descriptors figure 4-2 illustrates an example of sbd chaining. the host has formed a three-buffer message by linking three sbds. in this example, the sar transmits a message sequence of buffer a, then buffer b, and finally buffer c as the end of message. 4.2.2.4 transmit queues once the linked list of sbds is complete, the host submits the chained message to the sar for segmentation. the host uses one of the 32 transmit queues for this purpose. each transmit queue is a circular queue of one-word entries. the host identifies the next available transmit queue entry according to the write-only host interface specification described in section 3.3.1 . the host processor writes a pointer to the sar-shared memory sbd onto the next available transmit queue entry. during this write, the host also sets the vld bit to indicate the entry is valid. the cn8236 detects this write by snooping sar-shared memory accesses. when a write occurs to any of the transmit queues, the cn8236 marks that queue as pending. once every cell slot, the cn8236 services one queue entry from one transmit queue. the system designer selects one of two service order priority schemes. with the seg_ctrl(tx_rnd) bit set to 1, the cn8236 services queues in round-robin order (that is, one entry per queue in transmit queue sequence for all active queues). with the seg_ctrl(tx_rnd) bit set to 0, the cn8236 services the queues in fixed priority order (that is, entries from higher priority active queues are serviced before lower priority queue entries, with transmit queue 31 having highest priority). figure 4-2. segmentation buffer descriptor chaining sar shared memory host (or sar shared) memory vcc_index = 4 vcc_index = 4 control 4.0 segmentation coprocessor cn8236 4.2 segmentation functional description atm servicesar plus with xbr traffic management 4-6 mindspeed technologies ? 28236-DSH-001-B in either case, the sar services one transmit queue entry by linking the new buffer descriptor chain to the vcc table entry identified by the vcc_index in the first sbd. the vcc table entry includes pointers to buffer descriptors for segmentation. the sar links the new sbds to the current chain of sbds on a vcc. the host can submit data to a vcc while the sar is segmenting a previously submitted message. once the chain has been linked, the cn8236 resets the transmit queue vld bit to 0. sar transmit queue processing figures 4-3 and 4-4 illustrate the process of linking sbds to a vcc table entry. note: as the new buffers are submitted, the vcc is processing a single buffer pdu (bom/eom). the cn8236 accepts new pdus while it is processing outstanding buffers. figure 4-3. before sar transmit queue entry processing transmit queue entry vcc_index = 4 bd_pntr vcc state curr_descr last_descr vcc_index = 4 control cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.2 segmentation functional description 28236-DSH-001-B mindspeed technologies ? 4-7 4.2.2.5 partial pdus the host can submit partial pdus to the cn8236. in this case, the sar transmits the data and halts on a cell boundary. the partial pdu buffers are not required to be aligned to a cell boundary by the host. the cn8236 tracks the remaining segmentation data. if a partial cell remains, the cn8236 holds the buffer until it can complete a cell. once the host submits an additional buffer, the cn8236 resumes segmentation. 4.2.2.6 virtual paths for network management simplicity, the host can create virtual path vccs (that is, it can segment many vcis on one vp). the host supplies the vci for the atm header within each segmentation buffer descriptor (sbd). when using this method, the cn8236 must be provided with contiguous linked sbds that are of the same vcc_index (that is, the same vci) for the length of the pdu. this allows the cn8236 to multiplex vci messages at the pdu level. for aal5 segmentation, the host must guarantee that sbds are linked with pdu multiplexing to preserve cpcs-pdu integrity. figure 4-4. after sar transmit queue entry processing transmit queue entry vcc_index = 4 bd_pntr vcc state curr_descr last_descr vcc_index = 4 control 4.0 segmentation coprocessor cn8236 4.2 segmentation functional description atm servicesar plus with xbr traffic management 4-8 mindspeed technologies ? 28236-DSH-001-B 4.2.3 cpcs-pdu processing the buffers submitted by the user contain only user data, the cpcs service data unit (cpcs-sdu). the cn8236 adds the cpcs-pdu protocol fields to the cpcs-sdu. the sar supports three aal levels: aal5, aal3/4, and a transparent adaptation layer (aal0). specific features also allow the generation of oam cells. chapter 7.0 , covers oam generation in detail. 4.2.3.1 aal5 for aal5, the sar generates the cpcs-pdu trailer and pads the cpcs-sdu to align the pdu to a cell boundary. the cn8236 generates the pad, length (len), common part indicator (cpi), and cyclic redundancy check (crc) fields according to i.363. the host supplies the cpcs user-to-user indication (uu) field in the first buffer descriptor in a message, and the cn8236 transmits it following i.363. the sar generates the atm header according to host-initialized settings in the vcc table entry. the cn8236 terminates aal5 pdus by setting bit 0 of the payload type identifier field, pti[0] = 1. the host aborts pdus by activating an eom sbd abort option. the host activates this by setting the following fields in the seg buffer descriptor entry to these values: aal_mode = aal5 (b00), and aal_opt = abort (b01). figure 4-5 illustrates the cn8236 ? s aal5 pdu generation scheme. the sar uses internal circuits to generate and store pdu length and crc-32 in the seg vcc table. the cn8236 transmits these fields within the eom cell. the pad and cpi fields are generated internally. figure 4-5. aal5 cpcs-pdu generation user data buffer(s) h h h pad uu cpi len crc-32 uu atm_header pdu_len crc_rem seg vcc table entry internal byte length counter crc accumulator circuits (set pti[0] = 1) tx_fifo (1-9 cells) phy interface 8236_016 cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.2 segmentation functional description 28236-DSH-001-B mindspeed technologies ? 4-9 4.2.3.2 aal3/4 when a segmentation buffer descriptor ? s aal_mode field is set to aal3/4 (value = b10), the cn8236 generates the cpcs-pdu ? s cpi, btag, etag, basize, alignment (al), and length fields in the header and trailer of the cpcs-pdu and pads the pdu to align to a cell boundary. on the first cell of a buffer with bom set, the segmentation coprocessor generates the cpcs-pdu header fields as the first four bytes of the first sar-pdu ? s payload. on the last cell of a buffer with eom set, the segmentation coprocessor writes an all-0s pad field after the end of the segmentation buffer data to complement the cpcs-pdu payload to an integral number of four-byte words. the segmentation coprocessor then adds the 4-byte cpcs-pdu trailer and fills octets with 0s for the remainder of the sar-pdu payload. each cpcs-pdu field is generated as described in table 4-2 . the cn8236 also generates the sar-pdu ? s segment type (st), sequence number (sn), message identification (mid), length indication (li), and crc fields in each segmented cell for that cpcs-pdu. each aal3/4 cell carries 44 octets of payload and four octets (five fields) of header and trailer information. on the last generated cell for a cpcs-pdu with the eom set in the buffer descriptor, the segmentation coprocessor pads the sar-pdu payload with 0 to 44 bytes. table 4-2. aal3/4 cpcs-pdu field generation field # bits function cpi 8 common part identifier; set to 0. btag 8 beginning tag; read from seg vcc table entry. basize 16 buffer allocation size; read from seg buffer descriptor entry. al 8 alignment filler, aligns the trailer to fit a 32-bit word. etag 8 ending tag; read from seg vcc table entry. length 16 cpcs-pdu length; the calculated size of the pdu ? s payload. 4.0 segmentation coprocessor cn8236 4.2 segmentation functional description atm servicesar plus with xbr traffic management 4-10 mindspeed technologies ? 28236-DSH-001-B each sar-pdu field is generated as described in table 4-3 . table 4-4 shows the settings for the st (segment type) field. table 4-3. aal3/4 sar-pdu field generation field # bits function st 2 bom value for the first cell generated from the buffer with the bom option in the buffer descriptor set. eom value for the last cell generated from the buffer with the eom option in the buffer descriptor set. ssm value for the cell generated from the buffer with both bom and eom options in the buffer descriptor set, and the buffer descriptor length field 44. com value for all other generated cells. (see the next table for binary values.) sn 4 read from the sn field in the seg vcc structure. the sn field is incremented modulo 16 after each use. mid 10 read from the mid field in the seg vcc structure. li 6 generated by the segmentation coprocessor in an internal byte length counter. crc 10 generated as all zeros. the crc field can be overwritten with the crc-10 generator before transmission by setting the crc_10 option in the seg buffer descriptor. table 4-4. coding of segment type (st) field segment type encoding usage bom 10 beginning of message com 00 continuation of message eom 01 end of message ssm 11 single segment message cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.2 segmentation functional description 28236-DSH-001-B mindspeed technologies ? 4-11 figure 4-6 shows the cn8236 ? s aal3/4 pdu generation scheme. 4.2.3.3 aal0 the cn8236 also supports a transparent or null adaptation layer, aal0. aal0 maps cpcs-sdus directly to cpcs-pdu payloads. the sar pads the sdu to a 48-byte cell payload boundary, but generates no other overhead. the sar generates the atm header and pdu termination indications in the same manner as it does with aal5. figure 4-6. aal3/4 cpcs-pdu generation h st sn mid information li crc length etag al pa d trailer cpi btag basize <64 k header (44 bytes) payload convergence sublayer (cpcs-pdu) h st sn mid li crc h st sn mid li crc pad segmentation (sar-pdu) (to each seqmentented cell) (to each seqmented cell) seg vcc table entry tx_fifo (1-9 cells) phy interface internal byte length counter crc accumulator circuits atm_ header sn mid pdu_len betag 8236_094 note(s): 1. cpi = common part indicator. in aal3/4, initially set to all os. 2. btag = beginning tag. has the same identifying number as the etag field. when the receiver reassembles a long pdu, these tags help identify that cells are from the same pdu. 3. basize = buffer allocation size. tells the receiver how large the buffer allocation must be to receive and reassemble this pdu. 4. al = aligns the trailer to fit a 4-byte word. 5. etag = ending tag (see btag above). 6. length = contains the exact size of the pdu's payload. 4.0 segmentation coprocessor cn8236 4.2 segmentation functional description atm servicesar plus with xbr traffic management 4-12 mindspeed technologies ? 28236-DSH-001-B 4.2.4 atm phy layer interface once the segmentation coprocessor has formed an atm cell, the cn8236 transfers the cell to the transmit fifo buffer. the user chooses the length of this fifo buffer, with possible sizes from one to nine cells. the fifo buffer depth is programmable, since there is a trade-off between absorbing pci latency with a longer fifo buffer, and introducing greater jitter. section 6.2.3.3 , in the chapter 6.0 , discusses this trade-off in greater depth. once sent to the transmit fifo buffer, the cell passes through the fifo buffer to the phy layer interface circuits. 4.2.4.1 head-of-line flushing (holf) if the sar is set up as a utopia master in multi-phy operations, cells are transmitted to a phy device after the phy indicated that it can receive another cell by asserting its utopia clav signal. the utopia master waits until it receives the clav signal from the phy device, and therefore blocks the transmission of all other cells in the transmit fifo. if this phy device stops working, all other phy devices are blocked. this is called head-of-line blocking. in order to avoid head-of-line blocking in the transmit fifo, a mechanism to flush the blocking cell out of the transmit fifo is incorporated (head-of-line flushing). this mechanism is enabled by setting the tx_fifo_flush_en bit in the config1 register. when the utopia master puts out the address of a phy, a counter is reset to 0 and increased based on the utopia tx_clk. once the counter reaches the values tx_cntr set by the user in the csr register, the cell is discarded, and the bit corresponding to the blocking phy is set in the tx_port_status register. the counter is reset automatically. if any of the eight bits in the tx_status register is set, tx_discard in host_istat1 and lp_istat1 are set. if the corresponding mask bit en_tx_discard in host_imask1 or lp_imask1 is set, an interrupt is generated. the tx_discard is cleared once the tx_status register is read by the host. note: the cell discard does not disable the port. the user might decide to disable a specific port on the utopia interface. then all cells belonging to this port are discarded or flushed. ports are disabled by setting the corresponding bit in the tx_port_ctrl register. if a port x is disabled and a cell pertaining to port x is discarded, bit x in tx_status is not set, and therefore no interrupt is generated. for fault-tolerant multi-phy operations, a maximum tx_cntr value of 65,535 is recommended. for specific dsl applications with variable rate phy devices, a value between 50 and 100 is suggested. cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.2 segmentation functional description 28236-DSH-001-B mindspeed technologies ? 4-13 4.2.5 status reporting the cn8236 informs the host of segmentation completion using segmentation status queues. the host assigns each vcc to one of 32 status queues, enabling a multiple peer architecture as described in section 3.2 . the cn8236 reports status entry on either pdu or buffer boundaries, selectable on a per-vcc basis by setting the stm_mode bit. pdu boundary status is referred to as message mode, while buffer status reporting is called streaming mode. error conditions also generate status queue entries, though this is a rare occurrence within a cn8236 subsystem ? s segmentation block. the segmentation status queues operate according to the write-only host interface, defined in section 3.3.2 . the cn8236 returns a user-supplied field (user_pntr) from the first sbd associated with the status entry. the sar does not use this field for any internal purpose; it simply circulates the information back to the host. the value of user_pntr must uniquely describe the segmented buffer associated with the sbd. user_pntr can contain the address of the buffer or of a host data structure describing the buffer. to simplify host management, the cn8236 also returns the vcc_index of the vcc on which the buffer was transmitted. 4.2.6 virtual fifo buffers in addition to gathering pdu data from buffers, the cn8236 provides an optional method to segment from a fixed pci address, or virtual fifo buffer. the cn8236 supports aal0, cbr virtual fifo buffer segmentation. the host configures the channel for virtual fifo buffer operation by setting the curr_pntr and run fields to 0 in the seg vcc table entry. the host writes the fifo buffer address to the fifo_pntr field in the vcc table entry. the host also initially sets the sch_mode field = cbr. at this point the host can start writing cells to the external host transmit fifo buffer. once the fifo buffer is almost full, the host sets the run bit to a logic high. the sar then starts reading from the fifo buffer. when the fifo buffer gets below almost empty, the host sets the sch_opt bit to a logic high. the sar then skips a cell transmit opportunity in order to allow the fifo buffer to refill. after the sar skips a cell, it resets the sch_opt bit to a logic low. in this mode, the segmentation coprocessor reads 48 bytes of payload from the host fifo buffer, and prepends (that is, attaches to the beginning) the atm_header value in the vcc table entry. the host does not use the transmit queue for virtual fifo buffers. the cn8236 transmits cell payloads from this location indefinitely, with no status reporting. 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-14 mindspeed technologies ? 28236-DSH-001-B 4.3 segmentation control and data structures 4.3.1 segmentation vcc table entry each segmentation vcc table entry occupies one 10-word descriptor of the segmentation vcc table. the first 7 words are generic, independent of traffic class. the last 3 or 13 words provide additional parameters specific to service classes. there are two basic formats for the generic part of the vcc table entry: aal3/4-aal5-aal0 and virtual fifo buffer. each format completely describes the state of the segmentation process for individual vccs. table 4-5 and table 4-6 describe the format of aal3/4, aal5, and aal0 vcc table entries. key: = written by host at vcc setup = may be dynamically modified during active segmentation table 4-5. segmentation vcc table entry ? aal3/4-aal5-aal0 format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 pm_index rsvd ack_pm fwd_pm rsvd last_pntr 1 uu port_id bom_pntr 2 atm_header 3 pdu_len buffer_len 4 (1) crc_rem 4 (2) reserved betag rsvd sn mid 5 stm_mode stat/ hport_id pm_en last_clp run nx_eom rsvd curr_pntr 6 sch bck_pm vpc sch_gfr/cbr_w_tun flow_st gfr_pri sch_mode pri sch_opt next_vcc 7-9/19 sch_state note(s): (1) this word is used in aal5 and aal0 vccs. (2) this word is used in aal3/4 vccs. cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-15 table 4-6. segmentation vcc table entry ? aal3/4, 5, and 0 field descriptions (1 of 2) field name description pm_index performance monitoring index. 128 vccs can be selected for automatic oam pm generation. each monitored vcc has a unique performance monitoring index. if this field is changed while the vcc is active, only the byte containing the field should be written. (see chapter 6.0 .) ack_pm toggled after each backward reporting pm cell is sent. used to prevent pm information in pm table from being overwritten before cell is sent. fwd_pm indicates that next cell should be forward monitoring pm cell. last_pntr points to last buffer descriptor currently linked to the vcc. the two least significant bits of the pointer are assumed to be 0 (word-aligned). the address of the buffer descriptor is (last_pntr << 2) or (last_pntr x 4). uu aal5 user-to-user indication. this field is copied from the buffer descriptor uu field. the cn8236 inserts the uu field in the cpcs-pdu trailer contained in the eom cell. bom_pntr in message mode (stm_mode=0), points to the first buffer descriptor of a message composed of more than one buffer descriptor. the cn8236 returns the corresponding user_pntr from this buffer descriptor in the status queue. in streaming mode (stm_mode=1), it is not used. the two least significant bits of the pointer are assumed to be zero (word-aligned). the address of the buffer descriptor is (bom_pntr<<2) or (bom_pntr * 4). atm_header used for each atm cell for the vcc. the transmitted header may be modified by option bits in the current buffer descriptor. pdu_len cpcs-pdu trailer length field. this field is generated by the sar and inserted in the length field of the eom cell. buffer_len buffer length. the number of bytes of data read from the current segmentation buffer. port_id identifies the physical device (port) id for the vcc. crc_rem accumulated value of aal5 32-bit crc, calculated on-the-fly by the sar and appended to the pdu at eom. betag aal3/4 btag and etag fields. sn aal3/4 sequence number field. mid aal3/4 message id field. stm_mode streaming status mode. 0 = message mode ? a status entry is written (with a corresponding maskable interrupt) only when the last buffer in a message completes segmentation. the status entry written corresponds to the first buffer descriptor in the message. 1 = streaming mode ? a status entry is written (with a corresponding maskable interrupt) for each buffer as it completes segmentation. stat/hport_id identifies the segmentation status queue used for all status entries, or if the aalx_en bit is set, identifies the aalx port. pm_en enables performance monitoring for the vcc. if this bit is changed while the vcc is active, only the byte containing the bit should be written. (see chapter 7.0 .) last_clp last transmitted clp bit for vcc. this bit is updated by the src after each transmitted cell. this bit is in the same word as the pm_en bit, and is copied by the sar from the current buffer descriptor. the bit is used to select the correct vbr bucket for certain vbr vccs. 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-16 mindspeed technologies ? 28236-DSH-001-B run flag that indicates segmentation is proceeding. this flag is set to one by the sar when the host supplies data for the vcc; it is set to zero by the sar when the data available for the vcc is not sufficient to send an entire atm cell. nx_eom indicates that the next cell is the end of a cpcs-pdu. curr_pntr pointer to the current buffer descriptor for the vcc. this field is automatically updated by the sar. the two least significant bits of the pointer are assumed to be 0 (word-aligned). the address of the descriptor is (curr_pntr << 2) or (curr_pntr x 4). sch indicates vcc is currently scheduled for segmentation. bck_pm toggled after each backward reporting pm cell is scheduled. used to prevent pm information in pm table from being overwritten before cell sent. vpc on a vcc with sch_mode = abr this indicates a vp (instead of a vcc) connection, and rm cells are generated on vci = 6. sch_gfr/ cbr_w_tun if sch_mode = gfr, this bit set to a logic high indicates that the vcc is currently scheduled on a gfr_pri priority queue for segmentation. the sch bit set to a logic high indicates that the vcc is currently scheduled on a vbr priority queue. this host does not have to set this bit ? it is set by the sar. if sch_mode = cbr, this bit set to a logic high specifies that an unused cbr schedule slot should be used as a tunnel slot, with tunnel priorities specified in word 7 of the vcc table entry. flow_st flow control state. this bit is active only in er mode. indicates that the priority of the connection is increased to insure mcr. gfr_pri specifies the ubr priority level for a gfr service connection. gfr_pri must be < pri. sch_mode traffic class of vcc. (see chapter 6.0 , for details.) 000 ubr = unspecified bit rate 001 cbr = constant bit rate 010 = reserved 011 gfr = guaranteed frame rate 100 vbr1 = single leaky bucket vbr 101 vbr2 = dual leaky bucket vbr with both buckets always active 110 vbrc= dual leaky bucket vbr with bucket 1 applied only to clp = 0 cells 111 abr = available bit rate (as specified by tm 4.1) pri segmentation priority. the lowest priority is 0. the highest priority is 15. this field is not active when sch_mode is cbr. when sch_mode is gfr, this specifies the vbr priority. sch_opt schedule option. the use of this bit depends on the setting of the sch_mode field. vbr1, vbr2, vbrc, er: initializes bucket state to send maximum burst. the sar writes this bit to 0 after bucket state initialized. cbr: indicates that the next cell slot opportunity should be skipped. this bit is written by the host and cleared by the sar after the cell slot is skipped. if this bit is changed while the vcc is active, only the byte containing the bit should be written. next_vcc used by sar to link vccs in schedule chains. sch_state specific scheduling state information. the contents of this field depend on the setting of the sch_mode field. it is not used when sch_mode is set to ubr. (the contents of this field are detailed in chapter 6.0 .) table 4-6. segmentation vcc table entry ? aal3/4, 5, and 0 field descriptions (2 of 2) field name description cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-17 table 4-7 shows the format for virtual fifo buffer vcc table entries, including setup values for restricted fields. table 4-8 describes the field that differs from the aal3/4-aal5-aal0 format. table 4-7. segmentation vcc table entry ? virtual fifo buffers word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 pm_index reserved last_pntr 1 reserved reserved bom_pntr 2 atm_header 3 fifo_pntr 4 crc_rem 5 stm_mode stat pm_en reserved run=1 reserved curr_pntr= 0x00000 6 reserved sch_mode (=001 - cbr) pri sch_opt reserved 7-9/19 sch_state table 4-8. segmentation vcc table entry ? virtual fifo buffer format field descriptions field name description fifo_pntr pointer to the pci space data fifo buffer for cbr_fifo scheduling mode. 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-18 mindspeed technologies ? 28236-DSH-001-B 4.3.2 data buffers data buffers contain cpcs-sdus for segmentation and reside in host or sar-shared memory. the cn8236 retrieves host data buffers from any byte aligned pci address using the read multiple pci command. sar-shared data buffers must be aligned on word boundaries. buffers contain any number of bytes of only user data, up to a maximum of 64 kb. 4.3.3 segmentation buffer descriptors sbds reside in sar-shared memory on word-aligned addresses. the host controls the allocation and management of sbds. for each buffer to be segmented, the host utilizes one buffer descriptor from its pool of free descriptors. tables 4-9 through 4-13 describe the entry formats and field definitions for the sbds. table 4-9. segmentation buffer descriptor entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 (1) uu rsvd next_pntr rsvd 0 (2) basize_h rsvd next_pntr rsvd 1user_pntr 2 buffer_pntr 3 reserved local set_ci set_clp header_mod rpl_vci oam_stat gen_pdu crc10 aal_mode aal_opt cell bom eom length 4 misc_data seg_vcc_index note(s): (1) this version of word 0 is used for aal5 and aal0 vccs. (2) this version of word 0 is used for aal3/4 vccs. table 4-10. misc_data field bit definitions with header_mod bit set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 def. gfc_data reserved wr_gfc wr_pti wr_vci pti_data vci_data note(s): this definition of bits 31:16, misc_data field, applies when the header_mod bit is set, rpl_vci=0, and aal_mode is not = aal3/4; used when generating oam cells. cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-19 table 4-11. misc_data field bit definitions with rpl_vci bit set bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 def. new_vci note(s): this definition of bits 31:16, misc_data field, applies when the rpl_vci bit is set; used when identifying virtual channels under a vp vcc. table 4-12. misc_data field bit definitions with aal_mode set to aal3/4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 def. gfc_data reserved wr_gfc reserved basize_l note(s): this definition of bits 31:16, misc_data field, applies when the aal_mode field = aal3/4 and rpl_vci = 0. in order to activate gfc override, the header_mod bit must be set to a logic high. 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-20 mindspeed technologies ? 28236-DSH-001-B table 4-13. segmentation buffer descriptor field descriptions (1 of 3) field name description uu aal5 user-to-user indication. this field is copied to the vcc table entry uu field when bom is set and aal_mode is aal5. basize_h the high order bits used for the basize field in the aal3/4 header when the gen_pdu option is selected. next_pntr pointer to next buffer descriptor for the vcc. the two least significant bits of the pointer are assumed to be 0 (word-aligned). the host links segmentation buffer descriptors by writing this field to [(address of sdb)>>2] or [(address of sbd)/4] before submitting the chain on the transmit queue. the next_pntr of the last buffer descriptor in a chain is set to null (=0). user_pntr user data field returned in status entry. this field may equal buffer_pntr. the sar circulates this field back to the host in the status entry without using it internally. buffer_pntr pointer to segmentation buffer in host- or sar-shared memory space. host or sar-shared memory location is determined by the local bit. local 0 = buffer_pntr is a byte aligned pci address. 1 = buffer_pntr is a word-aligned address in sar-shared memory instead of host memory. set_ci 0 = the cn8236 generates bit 1 of pti[2:0] from the vcc table entry atm_header field. 1 = sets bit 1 of the atm header pti[2:0] field for all cells in buffer to 1. set_clp 0 = the cn8236 generates the clp bit from the vcc table entry atm_header field. 1 = sets the atm header clp bit for all cells in buffer to 1. also used to control vbr clp dual leaky bucket mode. header_mod 0 = the cn8236 ignores the wr_gfc, wr_pti, and wr_vci bits in this buffer descriptor. 1 = activates the wr_gfc, wr_pti, and wr_vci bits for this buffer descriptor. rpl_vci 0 = the cn8236 generates the vci field from the vcc table entry atm_header field. 1 = the cn8236 generates the vci field from the new_vci for all cells in the buffer. new_vci is also copied in to the vci portion of the atm_header field in the vcc entry. oam_stat buffer reports status to the global oam status queue seg_ctrl(oam_stat_id) instead of the stat specified in the vcc table entry. for message mode vccs (vcc table entry stm_mode = 0), the oam_stat bit of the last descriptor for the cpcs-pdu determines which queue to use (even though the first descriptor is returned in message mode). see chapter 7.0 ? oam for more details. gen_pdu 1 = generate aal3/4 header and trailer, or aal5 trailer. in aal3/4 mode, the sar-pdu is always gen- erated internally. crc10 overwrite last ten bits of each cell with crc10 calculation. used for oam and aal3/4 cells. aal_mode controls aal segmentation mode. 00 = aal5 01 = aal0 read 48-octet atm cell payload from segmentation buffer. only formatting is to set pti[0] on last cell of an eom buffer. 10 = aal3/4 11 = reserved cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-21 aal_opt options for aal_mode: for aal_mode = aal0 00 = normal operation 01 = single 10 = reserved 11 = reserved for aal_mode = aal3/4 or aal5 00 = normal operation 01 = abort single: length is ignored and 48-octets are read from buffer to form the payload of a single atm cell. vcc table entry crc_rem, buff_length, and pdu_length are not affected. by using the link_head bit in the transmit entry, the buffer descriptor is linked at the start of buffer descriptor chain for vcc. this means that there are no concerns with mid-cell insertion and that the cell has low latency. this is intended for oam cells. note: this option must be set in the buffer descriptor for any tx queue entry with link_head set. to do otherwise may result in corrupted seg data. abort: send aal3/4 or aal5 abort cell (no data is read from segmentation buffer). a buffer that has both abort and bom set is returned without sending an abort cell. cell 0 = cn8236 reads the 48-octet payload of atm cells from memory and generates the atm header internally. 1 = the cn8236 reads the entire 52-octet atm cell from segmentation buffer. the atm_header stored in the vcc table entry is not used in this mode, and aal_mode is ignored. bom 1 = buffer contains the beginning of a message. (see table 4-1 .) eom 1 = buffer contains the end of a message. (see table 4-1 .) length number of bytes of data contained in the segmentation buffer. local memory, non-eom buffer lengths must be multiples of 4 bytes (mod 4). maximum allowable size is 64 kb. gfc_data data for wr_gfc option. wr_gfc 0 = the cn8236 generates the gfc field from the vcc table entry atm_header field. 1 = the cn8236 overwrites the atm header gfc field for all cells in the buffer with gfc_data. global gfc changes (active for all buffers of vcc) can be set in the vcc table entry atm header. this bit is active only when header_mod is set. wr_pti 0 = the cn8236 generates the pti field from the vcc table entry atm_header field. 1 = the cn8236 overwrites the atm header pti field for all cells in the buffer with pti_data. the host can use this feature to generate f5 and pm oam cells. (see chapter 7.0 .) this bit is active only when header_mod is set. this bit disables pm tuc and bip16 calculations. wr_vci 0 = the cn8236 generates the vci field from the vcc table entry atm_header field. 1 = the cn8236 overwrites the atm header vci field for all cells in the buffer with (0x0000|vci_data). (msbs of vci are set to 0.) used to generate f4 oam cells. (see chapter 7.0 .) this bit is active only when header_mod is set. this bit disables pm tuc and bip16 calculations. pti_data data for wr_pti option. normally used to generate oam cells. vci_data data for wr_vci option. normally used to generate oam cells. new_vci data for the rpl_vci. the cn8236 overwrites the vcc table entry atm_header vci field with this data. therefore, the effect is permanent until the next buffer descriptor with rpl_vci is processed. table 4-13. segmentation buffer descriptor field descriptions (2 of 3) field name description 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-22 mindspeed technologies ? 28236-DSH-001-B basize_l the low order bits used for the basize field in the aal3/4 header when the gen_pdu option is selected. seg_vcc_index identifies the vcc entry in the vcc table. the cn8236 links this buffer descriptor to the identified vcc. table 4-13. segmentation buffer descriptor field descriptions (3 of 3) field name description cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-23 4.3.4 transmit queues 4.3.4.1 entry format the host submits chains of sbds to the cn8236 by writing a single word transmit queue entry. table 4-14 and table 4-15 describe the format of these entries. table 4-14. transmit queue entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vld link_head find_chain reserved seg_bd_pntr rsvd table 4-15. transmit queue entry field descriptions field name description vld 0 = entry invalid. waiting for the host to submit new data for segmentation. 1 = entry valid. the sar processes the entry when its read pointer into the queue advances to this entry. written to 1 by the host when submitting a new entry. the sar clears this bit to 0 when it has successfully linked the buffer descriptor chain to the vcc table. link_head 0 = the cn8236 links the new descriptor chain at the end of the existing chain on the vcc. 1 = the cn8236 links the new descriptor chain at the head of the existing chain. if this bit is set, the buffer must contain data for at least one cell. only a single buffer descriptor can be linked to a transmit queue entry when this bit is set. this bit is intended for use with the buffer descriptor single option to send in-line management cells with reduced latency. note(s): it is mandatory that the single option is set in the buffer descriptor for any tx queue entry with link_head set. to do otherwise may result in corrupted segmentation data. find_chain indicates the sar is searching for the end of the buffer descriptor chain. the host always writes this bit to 0. seg_bd_pntr points to the first buffer descriptor in the new buffer descriptor chain. bits 22:2 of the address are specified; the two least significant bits of the pointer are assumed to be 0 (word-aligned). 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-24 mindspeed technologies ? 28236-DSH-001-B 4.3.4.2 transmit queue management the transmit queues reside in a single continuous section of sar-shared memory. during initialization the host configures the number of entries per queue with the seg_ctrl(tr_size) field. the size ranges from 64 to 4,096 entries per queue. the host also selects a priority scheme at initialization with the seg_ctrl(tx_rnd) bit. both of these fields are static configurations and must not be changed during runtime operation. by initializing the seg_txbase register, the host determines the base address of all active transmit queues. this register contains the base address of the first queue, the number of active queues, and the write-only update interval for all queues. a set of other internal registers, the transmit queue base table entries, tracks the current state of the queues. table 4-16 and table 4-17 below describe the fields of these queues. the byte address of any transmit queue entry is given by: the host manages each transmit queue as an independent write-only control queue. chapter 3.0 describes the runtime management of a write-only control queue. the transmit queue base table contains all of the queue control variables except for interval, which is located in the seg_txbase register. (seg_txbase(seg_txb) 128) cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-25 4.3.5 routing tags based upon the setting of config1(tag_size) field, routing tags need to be prepended to the cell written into the txfifo. figures 4-7 through 4-9 show the routing tag tables and position in txfifo. the segmentation block writes either 4, 8, or 12 bytes into the txfifo, depending upon the size of tag required. the utopia block strips off the appropriate number of bytes to form the desired size cell. table 4-19 is a cross-reference between the routing tag table and the utopia cell. note: the maximum txfifo size becomes reduced when using routing tags. table 4-18. maximum txfifo size with routing tags tag size txfifo (maximum number of cells) 5 8 6 7 8 9 7 10 11 figure 4-7. route tag table for tag_size = 1 through 4 seg_tagbase(seg_tagb) b0 seg_vcc_index h0 h1 h2 0 31 txfifo h = atm header b3 b2 b1 b0 b3 b2 b1 h3 8236_017 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-26 mindspeed technologies ? 28236-DSH-001-B figure 4-8. route tag table for tag_size = 5 through 8 seg_tagbase(seg_tagb) 0 31 0x0 0x4 h0 h1 h2 txfifo h = atm header b0 b3 b2 b1 b4 b7 b6 b5 b0 b3 b2 b1 b4 b7 b6 b5 h3 seg_vcc_index 8236_018 figure 4-9. route tag table for tag_size = 9 through 11 seg_tagbase(seg_tagb) 0 31 0x0 0x4 txfifo h = atm header h0 h1 h2 b0 b3 b2 b1 b4 b7 b6 b5 b8 b11 b10 b9 b0 b3 b2 b1 b4 b7 b6 b5 b8 b11 b10 b9 h3 0x8 seg_vcc_index 8236_019 cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-27 table 4-19. routing tag cross-reference tag size b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 1 t1 2 t1 t2 3 t1 t2 t3 4 t1 t2 t3 t4 5 t1 t2 t3 t4 t5 6 t1 t2 t3 t4 t5 t6 7 t1 t2 t3 t4 t5 t6 t7 8 t1 t2 t3 t4 t5 t6 t7 t8 9 t1 t2 t3 t4 t5 t6 t7 t8 t9 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 11 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-28 mindspeed technologies ? 28236-DSH-001-B 4.3.6 segmentation status queues 4.3.6.1 entry format the cn8236 reports segmentation status to the host on one of 32 status queues. each entry on the queue is two words. tables 4-20 and 4-21 describe the format of a standard seg status queue entry. a second special status queue format for acr/er change notification is described in tables 4-22 and 4-23 . refer to section 6.3.7.5 for a description of the trigger mechanism for posting special status. table 4-20. segmentation status queue entry word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0user_pntr 1 vld ncr=0 stop done single ovfl i_exp i_man reserved seg_vcc_index table 4-21. segmentation status queue entry field descriptions field name description user_pntr copy of the user_pntr from the segmentation buffer descriptor. the sar circulates this field from the sbd without using it internally. in message mode, the sar returns the user_pntr of the bom buffer. in streaming mode, the sar returns the user_pntr of all buffers. vld 0 = entry invalid. indicates that the sar has not written the entry and the host should halt status processing. 1 = entry valid. indicates that the host may process the entry. written to 1 by the sar. written to 0 by the host. ncr when set to a 0, indicates a normal status queue entry. stop vcc has stopped because no more segmentation data is available. done set when buffer segmentation is complete and buffer is released to host. single set if single option is set in the segmentation buffer descriptor. ovfl overflow: status entry is last entry available. (see status queue overflow, below.) i_exp current i_exp rate parameter of the vcc. this field is written only when vcc_index(sch_mode) = abr. (see chapter 6.0 .) i_man the two msbs of the current i_man rate parameter for the vcc. this field is written only when vcc_index(sch_mode) = abr. (see chapter 6.0 .) seg_vcc_index segmentation vcc index on which the sar transmitted the buffer or pdu. cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-29 table 4-22. segmentation status queue format for acr/er word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0er acr 1 vld ncr=1 ncr_dir scr_not_dest reserved ovfl reserved seg_vcc_index table 4-23. status queue entry field descriptions for acr/er field name description er for src_not_dest = 0, reflects ta_er, current er field in bck rm cell. not valid for src_not_dest = 1. acr for src_not_dest = 0, reflects ta_ccr current ccr field in bck rm cell. for src_not_dest = 1, reflects current ccr field in fwd rm cell. vld entry valid. written to 1 by the src. written to 0 by the host. ncr when set to a 1, indicates that status entry is an acr notification status entry. src_not_dest a value of 1 indicates a source acr change notification. a value of 0 indicates a destination acr change notification. ncr_dir a logic high indicates latest ncr threshold crossed was ncr_hi, a logic low indicates ncr_lo threshold was crossed last. ovfl overflow: status entry is last entry available. seg_vcc_index segmentation vcc index for buffer. 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-30 mindspeed technologies ? 28236-DSH-001-B 4.3.6.2 status queue management at initialization, the host assigns the location and size of up to 32 queues by initializing internal registers, the segmentation status queue base table entries. the location and size of each queue is independently programmable via these base tables. the sar tracks its current position and the most recent known host position in the queues with fields in the base table entries. the host manages the queues as write-only status queues. the status queue base table entry contains all of the sar ? s write-only control variables. tables 4-24 and 4-25 describe the format of these entries. 4.3.6.3 status queue overflow since status queues contain a finite number of entries, it is possible that the sar will exhaust the available entries. although the sar handles this condition, the host should attempt to prevent overflows. the cn8236 detects when it writes the last available entry in a status queue (write = read_ud-1), and alerts the host to this condition by setting the ovfl bit in the status entry. until the host services the queue and increments the read_ud pointer in the base table register, the cn8236 inhibits segmentation on all channels that report on the overflowed status queue. all other channels are unaffected. table 4-24. segmentation status queue base table entry word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 base_pntr reserved local 1 size rsvd write reserved read_ud table 4-25. segmentation status queue base table entry field descriptions field name description base_pntr points (bits 31:2) to base of status queue. bits 1:0 are always 0 (word-aligned). local 0 = status queue located in pci address space. 1 = status queue located in sar-shared memory address space. this bit should be set to 0 for a write-only pci host architecture. size number of entries in this status queue: 00 = 64 01 = 256 10 = 1,024 11 = 4,096 write sar write pointer. represents the sar ? s current position in the queue. read_ud last update of the host processor read pointer. this field is written by the host processor. cn8236 4.0 segmentation coprocessor atm servicesar plus with xbr traffic management 4.3 segmentation control and data structures 28236-DSH-001-B mindspeed technologies ? 4-31 4.3.7 segmentation internal sram memory map as indicated in table 4-26 , the segmentation internal sram is in the address range 0x1400 ? 0x1617. the segmentation status queue base table registers (seg_st_qun) are in the address range 0x1400 ? 0x14ff. the internal transmit queue base table registers (seg_tq_qun) are in the address range 0x1500 ? 0x15ff. aalx registers are in the address range of 0x1600 ? 0x1617. other internal segmentation and scheduler registers are in the address range 0x1618 ? 0x17ff. table 4-26. segmentation internal sram memory map address name description segmentation status queue base table registers (seg_sq_qun): 0x1400 ? 0x1407 seg_sq_qu0 status queue 0 base table 0x1408 ? 0x140f seg_sq_qu1 status queue 1 base table ? ? ? 0x14f8 ? 0x14ff seg_sq_qu31 status queue 31 base table internal transmit queue base table registers (seg_tq_qun): 0x1500 ? 0x1507 seg_tq_qu0 transmit queue 0 base table 0x1508 ? 0x150f seg_tq_qu1 transmit queue 1base table ? ? ? 0x15f8 ? 0x15ff seg_tq_qu31 transmit queue 31base table 0x1600 ? 0x1603 aalx_ad0 pci address for aalx 0 connected to hfifowr0 0x1604 ? 0x1607 aalx_ad1 pci address for aalx 1 connected to hfifowr1 0x1608 ? 0x160b aalx_ad2 pci address for aalx 2 connected to hfifowr2 0x160c ? 0x160f aalx_ad3 pci address for aalx 3 connected to hfifowr3 0x1610 ? 0x1613 aalx_ad4 pci address for aalx 4 connected to hfifowr4 0x1614 ? 0x1617 aalx_ad5 pci address for aalx 5 connected to hfifowr5 4.0 segmentation coprocessor cn8236 4.3 segmentation control and data structures atm servicesar plus with xbr traffic management 4-32 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? 5-1 5 5.0 reassembly coprocessor 5.1 overview the reassembly (rsm) coprocessor processes cells received from the atm phy interface block. the coprocessor extracts the aal sdu payload from the received cell stream and reassembles this information into buffers supplied by the host system. the cn8236 supports aal5, aal3/4, and aal0 reassembly, and cell mode (1-cell pdus through a virtual fifo buffer, for cbr voice traffic). the cn8236 reassembles up to 64 k vccs simultaneously. individual connections are identified through separate vpi and vci index table structures. the vpi/vci index table mechanism provides very fast, consistent channel identification over the full range of vpi/vci addresses. cpcs-pdu payload data, the cpcs-sdu, fills the host-supplied data buffers assigned to each vcc. the host assigns each vcc to one or two of 32 independent buffer pools, from which the rsm coprocessor draws buffers as needed. the cn8236 extracts the cpcs-sdu from the cpcs-pdu, writes the sdu to host-supplied buffers, and performs all cpcs-pdu checks. the results of these checks and aal information are passed to the host on one of 32 independent status queues. this chapter provides information on the functions and data structures of the reassembly coprocessor. for detailed information on how the cn8236 handles pm cells, deals with oam functions, and interacts with the segmentation coprocessor in handling traffic management and scheduling, refer to chapter 6.0 , and chapter 7.0 . 5.0 reassembly coprocessor cn8236 5.2 reassembly functional description atm servicesar plus with xbr traffic management 5-2 mindspeed technologies ? 28236-DSH-001-B 5.2 reassembly functional description each cell received from the atm phy interface block belongs to any one of a possible 64 k virtual channels, or simultaneous messages. due to the asynchronous nature of atm, the cell contained in any incoming cell slot can belong to any vcc. thus, the reassembly coprocessor must assign each arriving cell to the proper vcc, thereby de-multiplexing the incoming messages. figure 5-1 illustrates the basic reassembly process flow. 5.2.1 reassembly vccs as with segmentation vccs, the cn8236 supports up to 64 k reassembly vccs, referenced by vcc_index, which identifies a location in the reassembly vcc table. each entry in the reassembly vcc table consists of 12 words and describes a single vc. each vc can be processed as either aal5, aal3/4, or aal0. aal0 vcs can optionally be treated as virtual fifo buffers. while the cn8236 accepts any reassembly vcc index within the range of 64 k vcc indexes, the actual number of reassembly vccs allowed by the sar is limited by the amount of sar-shared memory available in which to allocate and create rsm vcc tables, free buffer queues, rsm status queues, etc. figure 5-1. reassembly ? basic process flow messages (64 k) host atm cells atm network reassembly coprocessor 8236_020 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.2 reassembly functional description 28236-DSH-001-B mindspeed technologies ? 5-3 figure 5-2 illustrates how entries in the rsm vcc table are indexed by vcc_index. 5.2.1.1 relation to segmentation vccs the reassembly vcc index assignment is independent from the assignment of segmentation vcc indexes. a full duplex connection can have a segmentation vcc_index of 0x100, while its receive channel has a reassembly vcc_index of 0x800. this is especially important when a vp is represented by a single segmentation vcc_index, but each of its vcs is represented by its own distinct reassembly vcc table entry. for several operations, most notably abr, the cn8236 provides a method to associate a reassembly vcc with a segmentation channel. the seg_vcc_index field in the reassembly vcc table allows one or many reassembly channels to correlate to one specific segmentation vcc. figure 5-2. reassembly vcc table reassembly vcc table base register (rsm_tbase(rsm_vccb)<<7) vcc_index = 0 vcc_index = 4 vcc_index = 0xfffb vcc_index = 0xffff (64 k vccs) vcc table entry vcc table entry 12 words = 1 descriptor } 8236_021 5.0 reassembly coprocessor cn8236 5.2 reassembly functional description atm servicesar plus with xbr traffic management 5-4 mindspeed technologies ? 28236-DSH-001-B 5.2.2 channel lookup the cn8236 ? s reassembly coprocessor implements a vpi/vci index table mechanism using direct index lookup in order to assign each cell to a virtual channel, based on its vpi/vci value. each channel is thus identified by its internally generated index value, the vcc_index. this vpi/vci table index mechanism dynamically maps vpi/vcis to concatenated index values. it simplifies user channel assignment, provides flexible provisioning for received traffic, and provides fast, consistent lookup times regardless of the vpi/vci values. in addition, using vpi/vci table indexes minimizes the memory impact in pre-allocating large numbers of channels by requiring that only the vci index table entries be pre-allocated instead of the vcc table entries. figure 5-3 illustrates the direct index channel lookup mechanism. 5.2.2.1 programmable block size for vcc table/ vci index table some users might have a requirement or desire to limit the amount of memory allocated to vpi/vci channel lookup. to enable this, the cn8236 provides the user with the choice of enabling an alternative scheme for the memory allocation and table handling involved in the direct index lookup mechanism. in this scheme, the user programs the size of the memory block of rsm vcc table entries for all vci index table entries, to fit a range of 1 to 64 entries, instead of the default 64 entries. each rsm vcc entry requires 12 words of memory. by thus limiting the amount of memory space set aside for rsm vccs, the total memory space required for vcc allocation can be substantially lessened. to enable this scheme, set en_prog_blk_sz in the rsm_ctrl1 register to a logic high. the sar thus allocates block memory for vcc entries per vci, based on the value entered in vci_it_blk_sz (rsm_ctrl1). figure 5-3. direct index method for vpi/vci channel lookup base register (16) vpi index table vci index table vcc table rsm_tbase (rsm_vccb) vci_it_pntr vcc_block_index (for one vpi) vpi [11:0] vci [15:6] vci [5:0] (max. 1024 entries for each vpi) (block of 64 vcc table entries) rsm_tbase (rsm_itb) 8236_022 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.2 reassembly functional description 28236-DSH-001-B mindspeed technologies ? 5-5 the data structures that facilitate this scheme are illustrated in section 5.7.1 . figure 5-4 illustrates the alternate lookup mechanism. table 5-1 shows the relationships of the values in vci_it_blk_sz, and the values for the number of vci index table and vcc table entries per vci. figure 5-4. programmable block size alternate direct index method vci [x-1:0] base register (16) vpi index table vci index table reassembly vcc table vci_it_pntr vcc_block_index (for one vpi) vpi vci [15:x] (for x=0, pointer is not applicable) where x = value of vci_it_blk_sz 8236_103 table 5-1. programmable block size values for direct index lookup value of vci_it_blk_sz value of x vci index table portion of cell ? s vci number of possible vci index table entries per vpi vcc table portion of cell ? s vci number of possible vcc entries per vci index table entry 000 0 vci[15:0] 65536 (no pointer) 1 001 1 vci[15:1] 32768 vci[0] 2 010 2 vci[15:2] 16384 vci[1:0] 4 011 3 vci[15:3] 8192 vci[2:0] 8 100 4 vci[15:4] 4096 vci[3:0] 16 101 5 vci[15:5] 2048 vci[4:0] 32 110 6 vci[15:6] 1024 vci[5:0] 64 5.0 reassembly coprocessor cn8236 5.2 reassembly functional description atm servicesar plus with xbr traffic management 5-6 mindspeed technologies ? 28236-DSH-001-B 5.2.2.2 setup at system initialization, the user configures the cn8236 to comply with either the 8-bit uni vpi field or the 12-bit nni vpi field, by setting the rsm_ctrl0 (vpi_mask) bit to a logic high for uni operation or a logic low for nni operation. this configuration determines whether the cn8236 treats the upper nibble of the first header octet of each received cell as the gfc field (in the uni vpi definition), or as an extension of the vpi address. this gives an address range for vpis of either 256 entries (for uni) or 4096 entries (for nni), which sets the vpi index table size and dictates the number of vci index tables to be allocated. the user can also enable the programmable block size for vcc table entries as described in the section 5.2.2.2 by setting en_prog_blk_sz(rsm_ctrl1) to a logic high. at system initialization, the user can also limit the valid range of both vpi and vci addresses to be processed, in order to reduce the memory size of the lookup structures being accessed. vpis are limited by vp_en. vcis are limited by vci_range in the vpi index table entry and blk_en in the vci index table entry when en_prog_blk_sz is enabled. vpi/vci address pairs can now be pre-allocated in groups by mapping vci index table entries to blocks in the reassembly vcc table. once the reassembly process has been initiated, additional channels, switched virtual circuits (svcs), can be dynamically allocated with simple on-the-fly index updates. 5.2.2.3 operation upon reception of a cell, the reassembly coprocessor uses the vpi field as an index into the vpi index table, the base address of which is located at rsm_tbase(rsm_itb) x 0x80. the maximum allowed vpi value for uni header operation is 255, and the maximum allowed vpi value for nni operation is 4095, controlled by the rsm_ctrl0(vpi_mask) field. if the vpi_mask bit is a logic high (indicating uni header operation), the four most significant bits of the atm header are anded with 0000. the rsm coprocessor uses the vpi value to read the vpi index table entry. the vci_range field in the vpi index table entry is used to set the maximum allowed value of vci[15:x] values for that vpi, and thus sets the usable size of the vci index table for that vpi. if the value of vci[15:x] of the received vci field in the atm header is greater than the vci_range field in the vpi index table entry, or vp_en is a logic low, the reassembly coprocessor discards the cell and increments the cell_dsc_cnt counter. the vci_it_pntr indicates the base address of the vpi ? s vci index table. the cn8236 then reads the appropriate entry in the vci index table. the address of the vci index table entry is derived as follows: the vcc_block_index in the vci index table entry selects a contiguous block of 64 reassembly vcc state table entries (or from one to 64 vcc state table entries if en_prog_blk_sz is enabled), offset from the base address of the reassembly vcc table. the vcc_index value is derived by concatenating the vcc_block_index value with the vci[x-1:0] bits from the received cell header. thus, vci[x-1:0] from the received header points to the reassembly vcc state table entry for that vcc. vci_it_pntr 4 vci[15:x] 4 + vcc_index vcc_block_index vci[x-1:0] + = cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.2 reassembly functional description 28236-DSH-001-B mindspeed technologies ? 5-7 the reassembly coprocessor reads the first word of the vcc table entry. if vc_en is a logic low, the cell is discarded, and the cell_dsc_cnt counter is incremented. optionally, the counter is not incremented if the aal_type field has a value of 11. vc_en allows idle cells to be filtered if the phy layer has not already done so. if the channel is active, the cn8236 increments the cell_rcvd_cnt counter. 5.2.2.4 aal3/4 lookup aal3/4 mid multiplexing requires an additional level of indirection in channel lookup for received aal3/4 traffic. this is because one virtual connection can have a multiple number of connectionless messages (like smds datagrams) multiplexed onto that one received connection. each of these long sdus is identified by its mid value. thus, the vcc lookup also includes the mid value in the lookup mechanism. the vpi index table and vci index table lookup is performed exactly as described in section 5.2.2.4 . however, for aal3/4 connections, vcc_block_index + vci[5:0] points to an aal3/4 head rsm vcc table entry (see table 5-14 ). the aal3/4 head entry contains the vcc_index_base field which points to the first entry of a block of aal3/4 entries for one virtual connection, with the mid value = 0. vcc_index_base + mid points to the rsm vcc table entry for the received cell ? s virtual connection and mid. the aal3/4 lookup mechanism is illustrated in figure 5-5 . figure 5-5. direct index lookup method for aal3/4 base register (16) vpi index table vci index table reassembly vcc table rsm_tbase (rsm_itb) rsm_tbase (rsm_vccb) vci_it_pntr vcc_block_index vcc_index_base (for one vpi) vpi [11:0] vci [15:x] vci [x-1:0] mid (mid=0) (block of aal3/4 vcc table entries for 1 vc) (block of 2 x vcc table entries) 8236_023 5.0 reassembly coprocessor cn8236 5.2 reassembly functional description atm servicesar plus with xbr traffic management 5-8 mindspeed technologies ? 28236-DSH-001-B 5.2.2.5 variable vpi/port_id lookup (multi-phy support) in order to support multi-phy operation and/or reduce memory requirements of the vpi index table, a new variable vpi/port_id lookup mechanism has been implemented. this mechanism is enabled by setting rsm_ctrl1(en_vpi_size) = 1. when enabled, a new register called vpi_size determines the maximum allowable vpi on each port in binary increments up to 4095. in addition, the vpi can be turned off. figure 5-6 shows the vpi index table with config1(num_ports) = 4 and vpi_size = 0x000b_a09a. for all ports config1(num_ports), their vpi_size entry should be set to 0x0 in order to turn it off. figure 5-6. vpi index table with multiple ports rsm_tbase(rsm_itb) port_id = 0 (max_vpi = 1023) port_id = 1 (max_vpi = 511) port_id = 3 (max_vpi = 1023) 1024 entries 512 entries 1024 entries 2048 entries port_id = 2 (turned off) lecid/pmoam tables port_id = 4 (max_vpi = 2047) 8236_024 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.3 cpcs-pdu processing 28236-DSH-001-B mindspeed technologies ? 5-9 5.3 cpcs-pdu processing after the vcc has been identified via channel lookup, the reassembly coprocessor performs the appropriate cpcs-pdu processing according to the aal_type field in the reassembly vcc table. the reassembly process is essentially the extraction and concatenation of consecutive atm cell payloads on a specific vcc to form a cpcs-pdu. this processing is either reassembly into an aal5 pdu, according to the specification in ansi t1.635, reassembly into an aal3/4 pdu, or reassembly into a transparent aal0 pdu. the exact process is governed by the aal type described in detail in the subsections below. figure 5-7 illustrates the basic process function. setup each active reassembly vcc must have a corresponding entry in the reassembly vcc table to describe its state. at channel setup time ? either during system initialization for permanent virtual connections (pvcs), or dynamically for switched virtual connections (svcs) ? the host allocates a reassembly vcc table entry and configures the vcc according to its provisioned or negotiated characteristics. this includes the aal in use, its assigned buffer pools and allocation priority, and the associated segmentation vcc index (seg_vcc_index) for full duplex connections. operation once the reassembly process is activated, this rsm vcc table entry is used to track the current state of the connection and direct the cn8236 to perform specific functions as described throughout this chapter. figure 5-7. cpcs-pdu reassembly cpcs-pdu atm cells (hdr) (payload) . . . . . . (for a specific vcc) (hdr) (payload) (hdr) (payload) bom cell eom cell com cells . . . 8236_025 5.0 reassembly coprocessor cn8236 5.3 cpcs-pdu processing atm servicesar plus with xbr traffic management 5-10 mindspeed technologies ? 28236-DSH-001-B 5.3.1 aal5 processing except for the eom cell, all of the data within aal5 cell payloads is user data. the reassembly coprocessor writes all user data to memory as described in section 5.4 . the eom cell contains both user data and cpcs-pdu overhead, and delineates the end of an aal5 pdu. 5.3.1.1 aal5 com processing during reassembly of the pdu, the reassembly coprocessor calculates a crc-32 value on the received aal5 pdu, and counts the length of the pdu. the crc-32 value is collected in an accumulator, and the length value is collected in a length counter. after each received cell is processed, the reassembly coprocessor writes the crc-32 and length values to the reassembly vcc state table entry for that channel. 5.3.1.2 aal5 eom processing during reassembly of the aal5 pdu, certain bytes of the pdu other than user data are written to a status queue entry for that pdu. the rsm coprocessor writes these specific fields to the status queue entry: uu information cpi field length field figure 5-8 illustrates these process functions. when the eom cell is processed, the reassembly coprocessor performs the following checks: if the length field in the trailer of the aal5 pdu is 0, the reassembly coprocessor sets the abort bit in the status queue entry to a logic high. compares the calculated crcrem value to the crc-32 value in the trailer of the aal5 pdu. if different, the reassembly coprocessor sets the crc_error bit in the status queue entry to a logic high. compares the value collected in the length counter to the value in the length field in the trailer of the aal5 pdu. if the number of pad bytes is less than 0 or greater than the 47 the reassembly coprocessor sets, the pad_error bit in the status queue entry to a logic high. if the cpi field in the aal5 trailer is not 0, the cpi_error bit in the status queue entry is set to a logic high. all of the aal5 trailer information is also written into the end of the pdu buffer(s) in memory. figure 5-8. aal5 eom cell processing ? fields to status queue . . . . . . . . . atm cells eom cell aal5 pdu (user data) pad uu cpi length crc-32 status queue entry 8236_026 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.3 cpcs-pdu processing 28236-DSH-001-B mindspeed technologies ? 5-11 figure 5-9 illustrates these process functions. the cn8236 reports all pdu termination events, with or without errors, in a status queue entry for that channel. see section 5.6 for full details. 5.3.1.3 aal5 error conditions the user can set a global variable for the reassembly coprocessor, rsm_ctrl0 (max_len), dictating maximum sdu delivery length. the maximum allowable length, in bytes, of any aal5 cpcs-pdu, including trailer and pad, is during reassembly, this max_len value is checked to ensure that the pdu under reassembly does not exceed the maximum sdu delivery length. if the cn8236 receives a non-eom cell, where early packet discard is performed. the cn8236 reports this condition via a status queue entry, with the len_error and epd status bits set. the aal5_dsc_cnt counter is also incremented. refer to section 5.4.8 , for details on how this process is handled. for each eom cell where the pdu is completed, with ba_error status bit set. figure 5-9. aal5 processing ? crc and pdu length checks . . . (user data) cpi length status queue entry eom cell aal5 pdu pad atm cells uu rsm vcc table entry crc-32 accumulator (pad check) (compare) (not null) length counter crc-32 8236_027 min[rsm_ctrl0(max_len) 1024, 65568 tot_pdu_len 48 > max_len 1024 (or 65568) + tot_pdu_len 48 > max_len 1024 (or 65568) + 5.0 reassembly coprocessor cn8236 5.3 cpcs-pdu processing atm servicesar plus with xbr traffic management 5-12 mindspeed technologies ? 28236-DSH-001-B 5.3.2 aal3/4 processing the bom cell contains the header information for the aal3/4 pdu, and the eom cell contains the trailer information for the pdu. all of the other cell payloads for that pdu contain user data. the reassembly coprocessor writes all header, trailer, and user data to memory as described in section 5.4 . the eom cell contains both user data and cpcs-pdu overhead, and delineates the end of an aal3/4 pdu. the bom cell for a pdu sets the segment type (st) field in the cell to b10, and the eom cell sets the st field set to b01. all com cells set the st field set to b00. an st field value of b11 indicates a single segment message (ssm); that is, the cell holds all of a short pdu. figure 5-10 illustrates an aal3/4 cpcs-pdu reassembled from the received cell stream. figure 5-10. aal3/4 cpcs ? pdu reassembly aal3/4 cpcs-pdu <64 k cpi btag basize header payload pad pad al etag length trailer received cells (44 bytes) h st sn mid information li crc h st sn mid li crc h st sn mid li crc 8236_104 aal3/4 pdu fields: cpi = common part indicator. in aal3/4, initially set to all 0s. btag = beginning tag. has the same identifying number as the etag field. when the receiver reassembles a long pdu, these tags help identify that cells are from the same pdu. basize = buffer allocation size. tells the receiver how large the buffer allocation must be to receive and reassemble this pdu. al = aligns the trailer to fit a 4-byte word. etag = ending tag. (see btag above.) length = contains the exact size of the pdu's payload. aal3/4 atm cell fields: st = segment type. 10 = beginning of message, 00 = continuation of message, 01 = end of message, and 11 = single segment message. sn = sequence number. the cell number sequence within the pdu. cycles through 16 values. mid = message identification. allows many long sdus to be multiplexed onto a single stream of cells. the reassembly processor sorts cells by mid and reassembles pdus from cells with the same mid. li = length indication. dictates the length of pad of the sdu, to a multiple of four octets. crc = a crc check of the 48-byte atm cell payload. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.3 cpcs-pdu processing 28236-DSH-001-B mindspeed technologies ? 5-13 5.3.2.1 aal3/4 per-cell processing the following processing steps and checks occur on a per-cell basis: if the crc10_en bit in the aal3/4 head vcc table entry is a logic high, the crc10 field in the cell is checked. if in error, the sar increments the crc10_err counter in the vcc head table entry, and discards the cell. the mid field value is checked against active mid values specified by the mid_bits and mid0 fields in the aal3/4 head vcc table entry. if invalid, the sar discards the cell, and increments the mid_err counter in the vcc head table entry. if the cell is an eom cell and li = 63, the sar writes a status queue entry with abort bit set, cpcs_length=0, and bd_pntr pointing to the partially reassembled pdu. if the li_en bit in the aal3/4 head vcc table entry is a logic high, the li field is checked, and the following error detection and error processing is done: ? if the cell received is a bom, and li ? 44; the sar discards the cell, and increments the li_err counter in the vcc head table entry. ? if the cell received is a com, and li ? 44; the sar discards the cell, and terminates the current cpcs-pdu. the sar also writes a status queue entry with the li_error bit set, the cpcs_length = 0, and bd_pntr pointing to the partially reassembled pdu. the sar also increments the li_err counter in the vcc head table entry. ? if the cell received is an eom, and (li < 4 or li > 44); the sar discards the cell, and terminates the current cpcs-pdu. the sar also writes a status queue entry with the li_error bit set, the cpcs_length = 0, and bd_pntr pointing to the partially reassembled pdu. the sar also increments the li_err counter in the vcc head table entry. ? if the cell received is an ssm, and (li < 8 or li > 44); the sar discards the cell, and increments the li_err counter in the vcc head table entry. if the st_en bit in the aal3/4 head vcc table entry is a logic high, the st field in the cell is checked. the next_st field in the vcc entry is used for this check. a value of 01 in the next_st field indicates that the sar was expecting a bom/ssm cell. an 00 value indicates that the sar was expecting a com/eom cell. the following error detection and error processing is done: ? if the cell received is a bom, and the sar was expecting a com or eom, the sar terminates the current cpcs-pdu and writes a status queue entry with the st_error bit set, the cpcs_length = 0, and the bd_pntr pointing to the partially reassembled pdu. the sar also increments the bom_ssm_err counter in the vcc head table entry, and starts a new cpcs-pdu with the current bom cell. ? if the cell received is an ssm, and the sar was expecting a com or eom, the sar terminates the current cpcs-pdu, and writes a status queue entry with the st_error bit set, the cpcs_length =0, and the bd_pntr pointing to the partially reassembled pdu. the sar also increments the bom_ssm_err counter in the vcc head table entry, and processes the current cell as a valid cpcs-pdu. ? if the cell received is a com, and the sar was expecting a bom or ssm, the sar discards the cell. 5.0 reassembly coprocessor cn8236 5.3 cpcs-pdu processing atm servicesar plus with xbr traffic management 5-14 mindspeed technologies ? 28236-DSH-001-B ? if the cell received is an eom, and the sar was expecting a bom or ssm, the sar discards the cell, and increments the eom_err counter in the vcc head table entry. if the sn_en bit in the aal3/4 head vcc table entry is a logic high, the sn field in the cell is checked. if the cell received is an com or eom, and the sn field does not equal the next_sn field in the vcc table entry, the sar discards the cell, terminates the current cpcs-pdu, and writes a status queue entry with the sn_error bit set, cpcs_length = 0, and the bd_pntr pointing to the partially reassembled pdu. the sar also increments the sn_err counter in the vcc head table entry. 5.3.2.2 aal3/4 additional bom/ssm processing the cn8236 performs the following additional checks and functions on each bom or ssm cell received: when a bom cell is received for an aal3/4 cpcs-pdu (that is, with st field set to b10), the cn8236 checks if the cpi_en bit in the rsm aal3/4 head vcc table entry is set to a logic high. if so, the cpi field in the received cell is checked for a 0 value. if not a 0 value, the cn8236 treats this as an error condition and discards the cell, terminates the current cpcs-pdu, writes a status queue entry with the cpi_error bit set, and the cpcs_length and bd_pntr fields set to 0. cells up to and including the next eom are discarded. the cn8236 also checks if the bah_en bit in the rsm aal3/4 head entry is set to a logic high. if so, it checks if the basize field in the cpcs-pdu header is less than 37 octets, and if so, the cn8236 discards the current cell, terminates the current cpcs-pdu, and writes a status queue entry with the ba_error bit set, and the cpcs_length and bd_pntr fields set to 0. cells up to and including the next eom are discarded. if the cpi and basize fields are correct in the bom cell, the cn8236 copies the basize and btag fields into the vcc table entry for that mid, and sets the next_st and next_sn values in the vcc table entry. it also writes the cpcs-pdu header into the data buffer. if the li field in the sar-pdu > (basize+7), the sar discards the cell, terminates the cpcs-pdu, and writes a status queue entry with the len_error bit set and cpcs_length = 0. 5.3.2.3 aal3/4 additional com processing the cn8236 performs the following additional checks and functions on each com cell received: the cn8236 checks if the sum of the li fields for the cpcs-pdu are greater than (basize + 7). if so, the cn8236 discards the cell, terminates the cpcs-pdu, and writes a status queue entry with the len_error bit set high, cpcs_length set to 0, and bd_pntr pointing to the partially reassembled pdu. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.3 cpcs-pdu processing 28236-DSH-001-B mindspeed technologies ? 5-15 5.3.2.4 aal3/4 additional eom/ssm processing upon termination of a cpcs-pdu, the cn8236 performs the following additional checks and functions on each eom or ssm cell received: the length field in the cpcs-pdu trailer is written to the cpcs_length field of a rsm status queue entry written for the vcc. the cn8236 performs a pad length check to see if the sum of all lis for the cpcs-pdu ? length ? 8 = [0 to 3] octets. if in error, it sets the pad_error bit in the status queue entry. the cn8236 performs a modulo 32 bit check. if the sum of all lis for the cpcs-pdu is not modulo 32 bit, the sar sets the mod_error bit in the status queue entry. if the alignment (al) field in the cpcs-pdu trailer is not all 0s, it sets the al_error bit in the status queue entry. if the btag field in the rsm vcc table entry does not match the etag field in the cpcs-pdu trailer, it sets the tag_error bit in the status queue entry. the cn8236 checks the bat_en bit in the aal3/4 head vcc table entry. if bat_en is high, it compares the basize field to the length field in the cpcs-pdu trailer. if not a match, it sets the ba_error bit in the status queue entry. if bat_en is low, it checks if the length field is > basize; and if so, sets the ba_error bit in the status queue entry. the cn8236 writes the aal3/4 cpcs-pdu trailer to the data buffer. 5.3.2.5 aal3/4 mib counters whenever an aal3/4 mib counter rolls over to all 0s, the cn8236 writes a rsm status queue entry with the cnt_rovr bit set to a logic high, and the head_vcc_index field pointing to the aal3/4 head vcc entry which contains the rolled-over counter. this processing step takes place for the crc10_err, mid_err, li_err, sn_err, bom_ssm_err, and eom_err counters. 5.0 reassembly coprocessor cn8236 5.3 cpcs-pdu processing atm servicesar plus with xbr traffic management 5-16 mindspeed technologies ? 28236-DSH-001-B 5.3.3 aal0 processing aal0 is a transparent adaptation layer, allowing for pass-through of raw data cells during cpcs-pdu processing. aal0 channels are intended to be used for aal proprietary adaptation layers. 5.3.3.1 termination methods the cn8236 provides two methods of terminating an aal0 pdu: cell count eom and pti termination. the tcount field in the rsm vcc state table entry determines the method for each vcc. if tcount = non-0, cell count eom pdu termination is enabled. pdus terminate when a fixed number of cells (tcount) have been received. ccount must be initialized to a value of one in this mode. if tcount = 0, then pti termination is enabled. in this case, a received cell with pti[0] set to 1 indicates the end of the aal0 message. the total maximum allowable length of an aal0 pdu in this mode is (ccount 2) bytes. figure 5-11 provides an illustration of this. the cn8236 reports all pdu termination events, with or without errors, in a status queue entry for that channel. see section 5.6 . 5.3.3.2 aal0 error conditions if the cn8236 receives a non-eom cell in pti termination mode, where epd is performed. the cn8236 reports this condition via a status queue entry, with the len_error and epd status bits set. refer to section 5.4.8 , for details on how this process is handled. for each eom cell where the pdu is completed, with ba_error status bit set. the cn8236 processes error conditions for aal0 (such as free buffer queue underflow, status queue overflow, and per-channel buffer firewall), in the same way as aal5 cpcs-pdus are processed. figure 5-11. aal0 pti pdu termination (payload) (payload) (payload) . . . . . . . . . . . . atm cells aalo pdu (hdr) pti[0]=0 (hdr) pti[0]=0 (hdr) pti[0]=1 (eom cell) 8236_028 tot_pdu_len 48 > ccount 2 + tot_pdu_len 48 > ccount 2 + cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.3 cpcs-pdu processing 28236-DSH-001-B mindspeed technologies ? 5-17 5.3.4 atm header processing atm level ci and clp are mapped to the cpcs-pdu status queue entry in the following manner: lp: value of the atm header clp bit ored across all cells in a cpcs-pdu. ci_last: value of atm header pti[1] bit in last cell of cpcs-pdu. ci: value of atm header pti[1] bit ored across all cells in a cpcs-pdu. 5.3.5 bom synchronization signal the stat[1:0] output pins can be programmed to provide an indication that a bom cell is being written across the pci bus. additional external circuitry could snoop the bom cell for a service level protocol header and perform appropriate lookup as the cpcs-pdu is being reassembled. to configure the stat pins, set the statmode field in the config0 register to 0x00. the stat output truth table illustrated in table 5-2 . the stat output pins are valid during a sar pci master write address cycle. external circuitry would detect a bom cell transfer by detecting a logic high on either stat pin during a sar pci master write address cycle. external circuitry can then snoop the subsequent data cycles of the bom cell transfer to extract the appropriate protocol overhead. 5.3.5.1 prepend index in order to allow protocol processing to start upon reception of the bom cell, the vcc_index can be optionally prepended to the beginning of the bom cell. this, in conjuction with the bom sync signals via the stat pins, can be used to eliminate the need for a host lookup process before starting protocol processing. when rsm_ctrl0(prepend_index) is a logic high, the vcc_index is appended to the bom cell as follows: table 5-2. stat output pin values for bom synchronization stat[1] stat[0] not bom 0 0 aal5 bom 0 1 aal0 bom 1 0 not used 1 1 table 5-3. prepend index table format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved vcc_index 5.0 reassembly coprocessor cn8236 5.4 buffer management atm servicesar plus with xbr traffic management 5-18 mindspeed technologies ? 28236-DSH-001-B 5.4 buffer management once cpcs-pdu processing has been implemented, the cell payloads are written to data buffers. each channel retrieves the location of its buffers from one of 32 free buffer queues. the reassembly coprocessor tracks the location of the buffers from the vcc table entry for that channel. note: the process cycle time of a read transaction across the pci bus is much longer than a write transaction, due to the pci bus being held in a busy state while the remote processor accesses and processes the read request. therefore, to speed up processing flow during reassembly, the cn8236 uses only control and status writes across the pci bus between host and local systems. data buffers are supplied according to the mechanisms detailed below. 5.4.1 host vs. local reassembly data buffers can reside in both host and sar-shared memory. the majority of user data traffic should be reassembled in host memory. sar-shared memory reassembly is intended for low bandwidth management and control functions, such as oam and signaling. this allows an optional local processor to off-load these network management functions from the host, focusing host processing power on the user application. 5.4.2 scatter method the cn8236 uses an intelligent scatter method to write cell payload data to host memory. during reassembly to host memory, the reassembly coprocessor uses the dma coprocessor to control the scatter function. the reassembly coprocessor controls the incoming dma block during scatter dma to host memory. four data structures are maintained, as illustrated in figure 5-12 : two in the host memory, one in sar-shared memory, and one in internal memory. the linked cell buffers (hcell_buff) and reassembly buffer descriptors reside in host memory, and the free buffer queues (hfr_buff_qu) reside in sar-shared memory. the free buffer queues also have an associated free buffer queue base table. this table is in internal memory. the cn8236 allows for up to 32 independent free buffer queues. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.4 buffer management 28236-DSH-001-B mindspeed technologies ? 5-19 5.4.3 free buffer queues the free buffer queue structure consists of a free buffer queue base table, two base address registers, rsm_fqbase(fbq0_base and fbq1_base), and the corresponding free buffer queues. the reassembly vcc table entry for any channel contains two 5-bit fields: bfr0 and bfr1. these fields identify the free buffer queues that have been assigned to this channel by the host during initialization of the vcc table entry. bfr0 contains the bom free buffer queue number, and bfr1 contains the com free buffer queue number. typically, the bfr0 number is for free buffer queues 0 ? 15, and the bfr1 number is for free buffer queues 16 ? 31. the free buffer queue is configured in two banks. bank 0 contains free buffer queues 0 ? 15, and bank 1 contains free buffer queues 16 ? 31. the user can set bfr0 = bfr1 to disable this two-tier buffer structure. depending on the type of arriving cell (whether bom or com), the corresponding bfrx buffer number is used as an index to the appropriate free buffer queue base table entry. the base addresses for these banks are in rsm_fqbase(fbq0_base and fbq1_base). the reassembly coprocessor calculates the address of the first entry for any of the 32 free buffer queues as follows: each of the 32 free buffer queues is a circular queue whose entries are sequentially read by the sar. the reassembly coprocessor calculates the index for each sequential read as follows: the read field in the base table entry for any free buffer queue is the current read index pointer, and is continually updated with each read of that queue. each free buffer queue entry contains a pointer to a buffer descriptor (bd_pntr) and a pointer to a data buffer (buffer_pntr); when the free buffer queue entry is read, it returns those pointers. figure 5-12. host and sar-shared memory data structures for scatter method host sar-shared cell buffers buffer descriptors free buffer queues free buffer queue base table (inside the cn8236) 8236_029 fbqx_base [(size of each free buffer queue) bfrx mod 16] + (index of first entry for the queue) [(read index pointer) (size of each free buffer queue entry)] + 5.0 reassembly coprocessor cn8236 5.4 buffer management atm servicesar plus with xbr traffic management 5-20 mindspeed technologies ? 28236-DSH-001-B figure 5-13 illustrates this structure. refer to chapter 3.0 , for more information on the operation of the free buffer queue. figure 5-13. free buffer queue structure buffer_pntr b d _ p n t r rsm_fbq_qu0 0x1100 bfrx (bfr0 or bfr1) fbq base table (internal sram) [bfrx x (global size of fbq)] read (16 free buffer queues in each bank) free buffer queue bank 0 or 1 (sar-shared memory) fbqx_base 8236_030 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.4 buffer management 28236-DSH-001-B mindspeed technologies ? 5-21 5.4.4 linked data buffers after the free buffer queue has returned pointers to a buffer descriptor and a cell buffer, the reassembly coprocessor writes payload data to the buffer. the linked cell buffers contain the payload portions of the atm cells. the buffers do not contain any control information. a pointer in a separate buffer descriptor structure links the buffers. thus, the pointer in the free buffer queue (bd_pntr) points to a buffer descriptor, which has a pointer (buff_ptr) pointing to a buffer. the use of this buffer locating mechanism offers a layer of indirection in buffer assignment that maximizes system architecture flexibility. figure 5-14 illustrates this structure. the data buffers are linked by a pointer (next_pntr) in the first word of the buffer descriptor, which is written by the reassembly coprocessor when the current buffer is completed. the host writes the second word of the buffer descriptor to point to the next associated data buffer. the link pointer of the last buffer descriptor in a chain is written to null. the link pointer (next_pntr) is not written if the lnk_en bit in the rsm vcc table entry for that channel is a logic low. note: only the data buffers are affected by big/little endian processing. the buffer control structures (that is, the buffer descriptors, free buffer queue base table, and free buffer queues) are the same in both big and little endian modes. figure 5-14. data buffer structures buff_ptr next_ptr buff_ptr next_ptr buff_ptr null buffer descriptors (host memory) buffers (host memory) 8236_105 note(s): no user fields in buffers - payload data only. 5.0 reassembly coprocessor cn8236 5.4 buffer management atm servicesar plus with xbr traffic management 5-22 mindspeed technologies ? 28236-DSH-001-B 5.4.5 initialization of buffer structures before operation of the reassembly coprocessor is enabled, the host must initialize these buffer structures. the initialization in this section assumes that the firewall function is disabled (that is, rsm_fqctrl(fbq0_rtn) = 0), and therefore, all free buffer queue entries are two words. 5.4.5.1 buffer descriptors in every buffer descriptor entry, write the pointer to an available data buffer in the buff_ptr field. this assigns every data buffer to its own buffer descriptor. 5.4.5.2 free buffer queue base table allocate the size (in number of entries) of each of the 32 free buffer queues in the rsm_fqctrl register, (fbq_size) field, based on these values: 00 = 64 01 = 256 10 = 1,024 11 = 4,096 initialize the free buffer queue update interval, that is, how many buffers are taken off the free buffer queue before the cn8236 writes the current read index pointer to host memory. this is written to rsm_fqctrl(fbq_ud_int). initialize the forward, read, update, and empt fields in each free buffer queue base table entry to 0s. initialize the read_ud_ptr field in each base table entry with the appropriate address. write the appropriate length (in bytes) for the data buffers in that queue in the length field of each free buffer queue base table entry. initialize bfr_local and bd_local to the appropriate host/sar-shared memory locations. normally, both structures are in host memory. 5.4.5.3 free buffer queue entries write the base addresses of free buffer queues banks 0 and 1 in rsm_fqbase (fbq0_base and fbq1_base). for each allocated free buffer queue entry, write the bd_pntr and buffer_ptr fields corresponding to the buffer and buffer descriptor pair. also write the vld bit to a logic high. for each unallocated free buffer queue entry, write the vld bit to a logic low. 5.4.5.4 other initialization the user can globally disable free buffer underflow protection by setting rsm_ctrl(rsm_fbq_dis) to a logic high. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.4 buffer management 28236-DSH-001-B mindspeed technologies ? 5-23 5.4.6 buffer allocation the reassembly coprocessor performs buffer allocation when a new channel is being reassembled, or when a buffer on an existing channel in process of being reassembled, is full. the reassembly coprocessor reads the appropriate free buffer queue base table entry and free buffer queue entry. if the vld bit is a logic low, a queue empty condition has occurred. (the processing of this condition is described in section 5.4.7 .) if the vld bit is a logic high, the reassembly coprocessor uses the assigned buffer to store payload data. the vld bit is then written to a logic low without corrupting the bd_pntr value. the read index pointer and update counter are incremented. if the update counter equals rsm_fqctl(fbq_ud_int), the read index pointer is written to the location pointed to by read_ud_pntr, and the update counter is reset to 0. when the host wants to return a buffer to a free buffer queue, the host write index pointer is compared to the cn8236 read index pointer located at read_ud_pntr. if the write index pointer + 1 is equal to the read index pointer, an overflow condition has been detected, and further processing is halted. otherwise, the host writes and updates the free buffer queue entry with a new buffer pointer, buffer descriptor pointer, and vld bit set to a logic high. the host then increments its write index pointer. 5.4.7 error conditions an empty condition occurs when a buffer is needed and there are no available buffers in the free buffer queue. if the bfr1 queue is empty and bfr1 does not equal bfr0, the rsm coprocessor checks the bfr0 queue before declaring an empty condition. if an empty condition occurs after the first buffer of a cpcs-pdu is written, the reassembly coprocessor performs early packet discard on the channel and writes a status queue entry with the epd and free buffer queue underflow (undf) bits set to a logic high. epd functions are described in section 5.4.8 . also, if a buffer queue empty condition initially occurs at the beginning of a bom cell, a status queue entry is written with undf set to a logic high and bd_pntr null. in both cases, the rsm_hf_empt bit is set in the host_istat1 and lp_istat1 registers if the bd_local bit is a logic low in the free buffer queue base table, or the rsm_lf_empt bit is set if bd_local is a logic high. all cells of a pdu up to and including the next eom cell are discarded. upon receiving a bom or ssm cell, the reassembly coprocessor checks the queue indicated by bfr0 for a valid free buffer. if a free buffer exists, the rsm coprocessor stores the cell in the assigned buffer. for aal5 channels, the aal5_dsc_cnt counter is incremented for each cpcs_pdu discarded during this error condition. channels that have outstanding buffers from an empty queue are not affected until they need a new buffer. once the host has written more free buffers on the queue with vld bit set to a logic high, the reassembly coprocessor automatically recovers from the empty condition. 5.0 reassembly coprocessor cn8236 5.4 buffer management atm servicesar plus with xbr traffic management 5-24 mindspeed technologies ? 28236-DSH-001-B 5.4.8 early packet discard the packet discard feature provides a mechanism to discard complete or partial cpcs-pdus, based upon service discard attributes or error conditions. 5.4.8.1 general description the epd feature performs these basic functions: halts reassembly of the cpcs-pdu marked for discard until the next bom cell and the error condition has cleared. writes a status queue entry with the epd bit set and other appropriate status and pdu_checks bits set, based on the reason for the discard. 5.4.8.2 frame relay packet discard the frame relay discard attribute is contained in the bom cell of a cpcs-pdu. if the frd_en bit in the rsm vcc table is a logic high, the frame relay packet discard function for that vcc is enabled, and the functions below are performed: when the reassembly coprocessor receives a bom cell on a vcc with this feature enabled, it checks the 1-bit de field in the frame relay header. if this bit is a logic high, and the channel priority (the dpri in the rsm vcc table) is less than or equal to the global priority, rsm_ctrl (gdis_pri), the rsm coprocessor discards the cell, marks the rest of the packet for discard, and increments the serv_dis counter in the vcc table. all cells on that channel up to the next bom are discarded. if the serv_dis counter rolls over, the cnt_rovr bit in the next status entry for this channel is set to a logic high. the cnt_rovr bit in the vcc table holds this flag information until a status is sent. 5.4.8.3 clp packet discard if the clpd_en bit in the rsm vcc table is a logic high, the cell loss priority packet discard function for that vcc is enabled, and the following functions below are performed: when the rsm coprocessor receives a cell and this function is enabled, it checks the 1-bit clp field in the atm header. if this bit is a logic high, and the channel priority is less than or equal to the global priority, rsm_ctrl (gdis_pri), the rsm coprocessor discards the cell, marks the rest of the packet for discard, and increments the serv_dis counter in the vcc table. all cells on that channel up to the next bom are discarded. if the serv_dis counter rolls over, the cnt_rovr bit in the next status entry for this channel is set to a logic high. the cnt_rovr bit in the vcc table holds this flag information until a status is sent. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.4 buffer management 28236-DSH-001-B mindspeed technologies ? 5-25 5.4.8.4 lane-lecid packet discard ? echo suppression on multicast data frames the system designer can use this feature to discard superfluous traffic on the atm network caused by lan emulation clients (lecs) transmitting multicast frames, that is, point-to-multipoint emulated lan traffic. if the lecid_en bit in the rsm vcc table is a logic high, the lane-lecid discard function for that vcc is enabled, and the functions below are performed: the dpri field is used as an index into the lecid table. this allows support for up to 32 lecids, each a unique identifier for a single lan emulation client. when the rsm coprocessor receives a bom cell with this function enabled, it checks the 16-bit lecid field in the lane header against the value in the lecid table. if a match occurs, the rsm coprocessor discards the cell, marks the rest of the packet for discard, and increments the serv_dis counter in the vcc table. if the serv_dis counter rolls over, the cnt_rovr bit in the next status entry for this channel is set to a logic high. the cnt_rovr bit in the vcc table holds this flag information until a status is sent. 5.4.8.5 dma fifo buffer full the purpose of this function is to allow a graceful recovery from an incoming dma fifo buffer full condition. without this function, the reassembly coprocessor is stalled when the fifo buffer is full until recovery from the full condition. this causes the cells to be dropped indiscriminately on the upstream side of the reassembly block without any record of which vccs the cells belonged to. upon recovery from the full condition, cells belonging to corrupted pdus continue to be processed, which wastes pci bandwidth during the recovery phase. this function provides for a more efficient use of host and sar resources by allowing the reassembly block to process and drop cells during the full condition. the reassembly block marks all channels that receive a cell during the full condition for subsequent early packet discard. upon recovery from the full condition, the reassembly block performs early packet discard on the appropriate channels as cells are received on those channels. in addition, cells continue to be dropped on each channel until after an eom cell is received for that channel. early packet discard processing is delayed until recovery from the full condition, since the status entry also requires the use of the incoming dma fifo buffer. this function is enabled by setting the ff_dsc bit in each vcc entry to a logic high. the user can want to disable this function if the free buffers, buffer descriptors, and rsm status queues reside in sar-shared memory. similarly, if rsm_ctrl1(oam_qu_en) is a logic high, rsm_ctrl1 (oam_ff_dsc) should be set to a logic high. the user can want to disable this function if the global oam buffers, buffer descriptors, and status queues reside in sar-shared memory. early packet discard due to a fifo buffer full condition is indicated by the ffpd bit in the rsm status queue entry being a logic high. 5.0 reassembly coprocessor cn8236 5.4 buffer management atm servicesar plus with xbr traffic management 5-26 mindspeed technologies ? 28236-DSH-001-B 5.4.8.6 aal3/4 early packet discard processing the cn8236 performs epd for aal3/4 cpcs-pdus with these steps: sets the appropriate error bit in the pdu_checks field for a new rsm status queue entry. sets the cpcs_length field to 0. sets the bd_pntr field to point to the partially reassembled pdu. writes the status queue entry. discards all cells of that pdu up to and including the eom cell for that pdu. 5.4.8.7 error conditions partially reassembled cpcs-pdus is recovered for the following error conditions: non-eom max pdu length exceeded free buffer queue underflow status queue overflow cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.4 buffer management 28236-DSH-001-B mindspeed technologies ? 5-27 5.4.9 hardware pdu time-out the cn8236 automatically detects active cpcs-pdu time-out for reassembly channels. a pdu time-out occurs when a partially received pdu does not complete within a set time period. when it detects this time-out condition, the cn8236 provides a status queue indication to the host. this indication allows the host to recover the buffers held by the partially completed pdu. the cn8236 supports up to eight reassembly time-out periods. 5.4.9.1 reassembly time-out process a background hardware process performs the reassembly time-out function. the process is activated at a user-selected interval. the process is globally enabled by setting the gto_en bit in the rsm_ctrl0 register. once the rsm_to register is enabled, it controls the process activity. the process is activated every rsm_to_per rising edges of sysclk on cell boundaries. note: gto_en set to 0 resets the internal time-out interrupt counter. each time the process is activated, it examines a single vcc, identified by to_vcc_index. this is a 16-bit variable located at address 0x1350, in internal sram. the host should initialize this register to 0 at system initialization. to enable hardware time-out on an individual vcc, the host must set to_en in the vcc table entry. the host also assigns one of eight time-out periods to each vcc by initializing the to_index field in the vcc table entry. the cn8236 checks the to_en bit and the active pdu indicator bit, act_pdu, to see if time-out processing is enabled and necessary, respectively, for the current connection. if either bit is 0, to_vcc_index is incremented by 1 and compared to rsm_to_cnt in the rsm_to register. if to_vcc_index = rsm_to_cnt, to_vcc_index is reset to 0, and the time-out search is restarted at the beginning of the vcc table. if both bits are set, the cn8236 increments cur_tocnt in the rsm vcc table entry. it then compares cur_tocnt to the time-out value selected, term_tocntx, where x = to_index. term_tocnt0 through term_tocnt7 are located at address 0x1340 through 0x134c in internal sram. they must be initialized to appropriate values during system initialization. if cur_tocnt = term_tocntx, a time-out condition has occurred on the current vcc. the cn8236 follows the procedure described in section 5.4.9.4 . 5.4.9.2 halting time-out processing to halt time-out processing, the host ? must ? set the to_last bit to 1 in the rsm vcc table entry for the last vcc_index that the host needs enabled for time-out processing. when the cn8236 detects this bit set to 1, it halts time-out processing. when time-out processing is halted, the time-out process is still activated, but the vcc is not checked for a time-out condition. the cn8236 simply increments to_vcc_index and compares it to rsm_to_cnt. if they are equal, to_vcc_index is reset to 0, and the full time-out processing is re-enabled. 5.4.9.3 timer reset the cn8236 reassembly time-out process increments the cur_tocnt value. if it reaches a threshold value, a time-out condition has occurred. in aal5 and aal0, pti termination modes, the reception of a non-eom cell resets the counter. 5.0 reassembly coprocessor cn8236 5.4 buffer management atm servicesar plus with xbr traffic management 5-28 mindspeed technologies ? 28236-DSH-001-B 5.4.9.4 reassembly time-out condition the cn8236 reports reassembly time-out conditions via the vcc ? s reassembly status queue. the to bit in the status field of the status queue entry is set to 1. in message mode, the bd_pntr points to the beginning of the partial buffer descriptor chain. in streaming mode, the bd_pntr points to the last buffer descriptor in the chain. the only other valid fields in the status queue entry are vcc_index and vld. once status has been reported, the cn8236 re-initializes the vcc table entry to begin accepting a cpcs-pdu. 5.4.9.5 time-out period calculation the following equation determines the time-out period of a vcc: rsm_to_cnt must be greater than or equal to the maximum number of vccs that require time-out processing. 5.4.10 virtual fifo buffer mode this mode provides a logical fifo buffer port for cell data to host memory. its principal use is for aal0 cbr voice traffic. 5.4.10.1 setup to enable this mode on any channel, set fifo_en in the rsm vcc table to a logic high. the user initializes the cbuff_pntr field in the rsm vcc table to the address of the fifo buffer port. the channel should also be configured for aal0 fixed length termination mode, with a termination length of one cell. 5.4.10.2 operation whenever a buffer is required during reassembly in this mode, the cbuff_pntr address is used without accessing the free buffer queue. no status entries are written in this mode because there is no way to maintain synchronization between status entries and cells in the fifo buffer under fifo buffer overflow conditions. 5.4.10.3 errors when the fifo buffer port is on the pci bus, the cbuff_pntr address must be on a 64 byte boundary and a decode of any address in the 64 byte block accesses the fifo buffer. external circuitry must also ensure that only complete cells are written into the host fifo buffer. the beginning of a cell transfer can be detected by the pci address being 64-byte aligned. period sysclk period rsm_to_per rsm_to_cnt term_tocntx = cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.4 buffer management 28236-DSH-001-B mindspeed technologies ? 5-29 5.4.11 firewall functions implementation of multiple free buffer queues and epd performs a firewalling functionality on a group basis. the user can also set up per-vcc firewalling on a channel-by-channel basis. the firewall mechanism allows the user to allocate buffer credits on a per-channel basis. note: when firewalling is enabled in the rsm coprocessor and an fbq empty (underflow) condition is encountered, the rx_counter field in the vcc table(s) still decrements each time the vcc receives a bom cell. the rx_counter should not be decremented when the fbq is empty. there is no workaround for this problem. the user ? must ? avoid fbq empty conditions when firewalling is enabled. 5.4.11.1 setup set rsm_fqctrl(fbq0_rtn) to a logic high. this sets free buffer queue block 0 to contain queues with 4-word entries. this is used to support per-vcc firewall credit update. set the global firewall control bit to a logic high in register rsm_ctrl0, field (fwall_en), to globally enable firewall processing on a per-channel basis. set the following fields of the vcc table entry for the channel being set up for firewall processing: the fw_en bit set to a logic high enables firewall processing on that channel. set rx_counter[15:0] to assign the initial buffer credit for the channel. initialize the forward fields in the free buffer queue base tables to point to the entry where credit is initially returned. typically, this is the first entry after the initial buffers placed on the queue. write the fwd_vld bit in all free buffer queue entries to a logic low. 5.4.11.2 operation whenever a buffer is taken off free buffer queues 0 through 15 during reassembly on a channel enabled for firewall processing, the rsm coprocessor decrements the rx_counter[15:0] in the rsm vcc table entry for that channel. this allows com buffers to be placed on queues 16 through 31 without being firewalled. if the rx_counter[15:0] for a channel is 0 when a buffer is required, the rsm coprocessor declares a firewall condition. if the firewall condition occurs on a bom or ssm, the cn8236 writes a status queue entry with the fw bit set and a null in the bd_pntr field. if the firewall condition occurs on a com or eom, the rsm coprocessor initiates epd and writes a status queue entry with the fw and epd bits set. it then discards cells on that channel until the channel has recovered from the firewall condition. all aal5 pdu ? s discarded under the firewall condition cause the aal5_dsc_cnt counter to be incremented. recovery occurs only on a bom or ssm cell when the credit is rechecked. 5.4.11.3 credit return the user returns credit, at the same time the buffer is recovered to the free buffer queue, by writing the third word of the free buffer queue. the vcc_index is written to the channel to which credit is returned. the fwd_vld bit is set to a logic high, and the qfc bit is set to a logic low. the rsm coprocessor increments 5.0 reassembly coprocessor cn8236 5.4 buffer management atm servicesar plus with xbr traffic management 5-30 mindspeed technologies ? 28236-DSH-001-B the rx_counter[15:0] of the applicable channel. for proper operation of the update interval function, buffers must be returned at the same time as credits are returned. credits are returned to vccs through bank 0 free buffer queues. in order to return buffer credits independently from buffer usage, the cn8236 maintains a separate read pointer into free buffer queues that return credits. this pointer name is forward, located in the free buffer queue base table entry. the host determines the number of bank 0 free buffer queues that return credits by setting fwd_en in the rsm_fqctrl register. the cn8236 snoops writes to free buffer queues that return firewall credits. when a write completes, the cn8236 begins processing firewall return credits on that queue. the third word of each entry is read, and if fwd_vld is set, a credit is added to the vcc_index indicated. the cn8236 continues to process credit return entries until fwd_vld is zero. multiple free buffer queues might have credit return entries outstanding at one time. the cn8236 processes the entries according to the priority set in fwd_rnd in the rsm_fqctrl register. if fwd_rnd is a logic low, the cn8236 exhausts the credit returns on the highest number active queue before proceeding to other queues. otherwise, it services the queues in round-robin order. before the reassembly coprocessor is enabled, the host must initialize the forward read pointer to the first entry where credit is returned. typically, this is the first entry after the initial buffers placed on the queue. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.5 global statistics 28236-DSH-001-B mindspeed technologies ? 5-31 5.5 global statistics to meet the requirements of ilmi (atm forum) and atom (rfc1695) documents, three register-based counters are implemented: cell_rcvd_cnt ? number of cells received that map to active channels. cell_dsc_cnt ? number of cells received that map to inactive channels. this includes idle cells, since those channels is turned off. aal5_dsc_cnt ? number of aal5 cpcs-pdus discarded due to per channel firewall, buffer queue underflow, fifo buffer full packet discard, status queue overflow, or maximum cpcs-pdu length exceeded on non-eom cells. the first two counters are implemented as 32-bit counters, and the third is a 16-bit counter. all three are set to 0 upon a reset and are not reset to 0 upon a read of the counter by the host. the counters roll over and optionally cause an interrupt upon rollover. 5.0 reassembly coprocessor cn8236 5.6 status queue operation atm servicesar plus with xbr traffic management 5-32 mindspeed technologies ? 28236-DSH-001-B 5.6 status queue operation the cn8236 reports reassembly status to the host via the reassembly status queue. the reassembly coprocessor normally writes a status queue entry when a complete cpcs-pdu has been reassembled. one field of the status queue entry (bd_pntr) points to the first buffer descriptor in the linked list of buffer descriptors for that reassembled pdu, and the rest of the fields of that status queue entry provides data on the status of the reassembled pdu. these fields are then used by the host in directing further processing. 5.6.1 structure two data structures are maintained as illustrated in figure 5-15 , one in host memory and one in sar-shared memory. the status queues (hstat_qu) reside in host memory, and the status queue base table resides in sar-shared memory, and allows for up to 32 independent circular status queues. the status queue base table is located at 0x001000 in internal sram. the status queue base table contains status queue base information for up to 32 queues. the queues are accessed via a status pool number, the stat field in the rsm vcc table. this field is used as an index to the correct status queue base table entry. the base_pntr field in the status queue base table entry points to the base address of the status queue associated with that status queue base table entry. the write field is the index pointer maintained by the cn8236, incremented each time a status queue entry is written, to point to the next status queue entry for that status queue. figure 5-15. data structure locations for status queues host sar-shared status queue base table (internal in the cn8236) 8236_031 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.6 status queue operation 28236-DSH-001-B mindspeed technologies ? 5-33 figure 5-16 illustrates this structure. 5.6.1.1 setup at system initialization, set up the following fields in each of the status queue base table entries: write the base address of the corresponding status queue in the base_pntr field. initialize the write and read_ud fields to 0s. set the size field for the size of the corresponding status queue. set the local bit to a status high if the status queue is in local memory; otherwise set the bit to a logic low. in addition, initialize each status queue entry in all 32 status queues by setting the vld bit to a logic low. initialize the read pointers to 0 for each status queue. figure 5-16. status queue structure format stat (from rsm vcc table entry) status queue base table (internal sram) (32 entries in the base table) write (32 status queues) base_pntr 0x1000 b d _ p n t r 8236_032 5.0 reassembly coprocessor cn8236 5.6 status queue operation atm servicesar plus with xbr traffic management 5-34 mindspeed technologies ? 28236-DSH-001-B 5.6.1.2 operation the reassembly coprocessor normally writes a status queue entry when a complete cpcs-pdu has been reassembled. it also writes a status queue entry for each received oam cell. each time the rsm coprocessor writes a status queue entry, it sets the vld bit in the entry to a logic high and increments the write pointer in the status queue base table entry for that status queue. when the host processes the status queue, it reads entries based on the host read pointer for that status queue. it reads only the vld bit at first before reading any other word to maintain data coherency. when the host finds the vld bit set to a logic high, it processes the status queue entry, increments the host read counter, and resets the vld bit to a logic low. the host also periodically writes the read counter value to the read_ud field in the status queue base table entry for that queue. when in message mode, the rsm coprocessor writes a status entry at the completion of a cpcs-pdu. optionally, a status entry can be written at both the beginning and end of a message to allow the host to initiate protocol header processing in advance of receiving the complete message. the host can then traverse the linked cell buffers to collect the complete cpcs-pdu. if the bintr bit in the rsm vcc table entry is a logic high, the rsm coprocessor writes an additional status queue entry at the completion of the first buffer of a cpcs-pdu. this status queue entry is delineated by the bom bit set and the eom bit cleared. this allows the host to begin packet processing before reception of the complete cpcs-pdu. in this case only the bd_pntr and vcc_index fields are valid in that status queue entry. the stm_mode bit in the rsm vcc table, being set to a logic high, activates streaming mode for that channel. in this mode, the rsm coprocessor writes a status entry for each completed buffer. the bd_pntr field in the status entry points to the corresponding buffer descriptor for that single buffer. only the last status entry for that cpcs-pdu, with eom bit a logic high, contains valid status data for that pdu. refer to chapter 2.0 , for detailed information on the operation of status queues. 5.6.1.3 errors the rsm coprocessor also writes a status entry for several error conditions: reassembly time-out early packet discard per-channel firewall cpcs abort to ensure that an error indication occurs even if no cpcs-pdus are being reassembled on channels having free buffer queues in the empty state, a bom cell causes a status queue entry to be written. if a bom cell is received and no early packet discards have occurred on channels mapped to the empty free buffer queue, status queue entry is written with the bom and undf bits set to a logic high. in addition, either the rsm_hf_empt bit in the host_istat1 register or the rsm_lf_empt bit in the lp_istat1 register is set to a logic high. this status does not point to a linked list of buffer descriptors. it is written a maximum of once per free buffer queue empty condition. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.6 status queue operation 28236-DSH-001-B mindspeed technologies ? 5-35 5.6.1.4 host detection of status queue entries the host can use either a polling operation or an interrupt routine to detect new status queue entries. to poll each status queue, the host continuously reads the vld bit at the current read position until it returns a logic high. the host then processes the status entry, writes the vld bit to a logic low, and increments its current read pointer. periodically, the host writes the current read index value into the read_ud field of the status queue base table entry. the host can also use an interrupt routine to process status queues. when the reassembly coprocessor writes a status queue entry into host memory, the host_istat0 (rsm_hs_write) bit is set to a logic high to prompt an interrupt. upon receiving an interrupt, the host reads host_st_wr (rsm_hs_write[15:0]) to determine which host memory status queue(s) caused the interrupt. note: only status queues 0 through 15 are reported in this register. a typical operation for the interrupt manager is to only read host_istat1 upon receiving an interrupt, and periodically read host_istat0 to ensure that no error conditions have occurred. once the interrupt manager has determined which status queue(s) caused the interrupt, the host starts reading the appropriate status queues at their current read location. the host processes status entries until reading an entry with the vld bit set to logic low. again, the host periodically writes the current read index value into the read_ud field of the status queue base table entry. 5.0 reassembly coprocessor cn8236 5.6 status queue operation atm servicesar plus with xbr traffic management 5-36 mindspeed technologies ? 28236-DSH-001-B 5.6.2 status queue overflow or full condition a status queue overflow or full condition is entered when the last available status queue entry is written. the reassembly coprocessor detects the condition by comparing the write+1 and read_ud index pointers. if the pointers are equal, a status overflow condition is detected and the rsm coprocessor sets the internal ovfl bit in the last status queue entry written to a logic high, to indicate the condition. the rsm coprocessor also sets to one either the rsm_hs_full bit in the host_istat1 register, or the rsm_ls_full bit in the lp_istat1 register, to prompt an interrupt. while the reassembly coprocessor is in status-full condition, it discards all cells. if a com or eom cell is received while the status queue is full, the channel is marked for status-full packet discard. once an ssm, eom, or oam cell is received during a status-full condition, the cell is discarded and the status queue checked. if there is now room in the status queue, the status-full condition is exited. for multiple peer configurations, the user can configure an interrupt manager to detect the full condition and advise the peers to check if their queues have overflowed. each peer would then check the ovfl bit in the last status queue entry written (pointed to by read_ud ? 1), to determine if that peer ? s status queue has filled. if the ovfl bit is not set to a logic high, the host should also check the entry pointed to by (read_ud2 ? 1) to determine if an overflow condition occurred during a host update of the read_ud index pointer. because the reassembly coprocessor recovers from the overflow condition automatically, the host does not have to determine which queue overflowed. after a status group has exited a full condition, the rsm coprocessor performs epd on channels marked for packet discard due to the status overflow condition, when a cell is received on any of those channels. cells up to and including the next eom are discarded. status queue overflow protection can be globally disabled by setting rsm_ctrl0(rsm_stat_dis) to a logic high. note: avoid having the status queue overflow (or full condition) and dma fifo buffer full conditions at the same time. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-37 5.7 reassembly control and data structures 5.7.1 channel lookup structures the reassembly coprocessor utilizes a vpi/vci table index mechanism employing direct index lookup in order to assign each arriving cell to a virtual channel, based on its vpi/vci value. figure 5-17 illustrates this lookup mechanism. table 5-4 describes the normal vpi index table format (one word per entry) without en_prog_blk_sz (rsm_ctrl1) enabled. table 5-5 describes the vpi index table format (two words per entry) with programmable vcc table and vci index table block size enabled. table 5-6 describes the field definitions for the vpi index table fields. figure 5-17. vpi/vci channel lookup structure base register (16) vpi index table vci index table (for one vpi) rsm_tbase (rsm_itb) vpi [11:0] vci [15:x] vci_it_pntr vcc_block_index (either 256 or 4096 entries) where x=6; or value of vci_it_blk_sz with en_prog_blk_sz enabled 8236_106 table 5-4. normal vpi index table entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vp_en vci_range vci_it_pntr table 5-5. vpi index table entry format with en_prog_blk_sx(rsm_ctrl1) enabled word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vp_en reserved vci_it_pntr 1 reserved vci_range 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-38 mindspeed technologies ? 28236-DSH-001-B table 5-7 describes the vci index table format without the programmable vcc table and vci index table block size enabled. table 5-8 describes the vci index table format with en_prog_blk_sz (rsm_ctrl1) enabled. table 5-9 describes the vci index table descriptions. table 5-6. vpi index table entry descriptions field name description/function vp_en enables the vpi for lookup processing. if not enabled, cell is discarded, and the cell_dsc_cnt counter is incremented. vci_range determines the maximum vci value allowed. if cell vci exceeds maximum, cell is discarded and counted as cell_dsc_cnt. in normal operation, the 10 most significant bits can be set by the user, with the six least significant bit set at 1. when en_prog_blk_sz(rsm_ctrl1) is enabled, all 16 bits of the field can be set by the user. vci_it_pntr vci index table base pointer. points to the base of the vci index table for the vpi by appending two least significant 0 bits to form a byte address. table 5-7. normal vci index table format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved vcc_block_index reserved table 5-8. vci index table format with en_prog_blk_sz (rsm_ctrl1) enabled word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 blk_en reserved vcc_block_index table 5-9. vci index table descriptions field name description/function blk_en block enable. if logic high, enables entry. if a logic low, the cell is discarded. vcc_block_index vcc block index. when en_prog_blk_sz is not enabled, this is the index to the block of 64 rsm vcc table entries allocated to vci[15:6]. in this case, vcc_block_index is concatenated with the six least significant bits of the vci to form the index into the rsm vcc table to access the vcc table entry for that channel. when en_prog_blk_sz is enabled, the [16 ? (value of vci_it_blk_sz)] most significant bits of vcc_blk_index are concatenated with the [(value of vci_it_blk_sz) ? 1] least significant bits of the vci to form the index into the vcc table to access the vcc table entry. for example, if the value of vci_it_blk_sz = 4, the resultant rsm vcc_index pointer = {vcc_blk_index[15:4], cell_vci[3:0]}. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-39 5.7.2 reassembly vcc table each reassembly vcc table entry occupies one 12-word descriptor of the reassembly vcc table. there are three basic formats for the reassembly vcc table entry ? aal5, aal0, and aal3/4. each completely describe the state of the reassembly process for individual vccs. in addition, the aal3/4 head vcc table entry describes the aal3/4-specific reassembly process state for an aal3/4 vcc. figure 5-18 illustrates the vcc table entry lookup mechanism as a continuation from figure 5-17 . figure 5-18. reassembly vcc table entry lookup mechanism base register rsm_tbase(rsm_vccb) vcc_block_index vci[5:0] 8236_033 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-40 mindspeed technologies ? 28236-DSH-001-B 5.7.2.1 aal5, aal0 and aal3/4 vcc table entries table 5-10 describes the format of aal5 reassembly vcc table entries. table 5-11 describes the format of aal0 rsm vcc table entries. table 5-12 describes the format of aal3/4 rsm vcc table entries. key: = written by host at vcc setup. = may be dynamically modified during active reassembly. table 5-10. reassembly vcc table entry format ? aal5 word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vc_en aal_type dpri reserved pass_oam reserved ff_dsc to_index pm_index aal_en 1 to_last to_en cur_tocnt er_efci reserved abr_ctrl 2 pdu_flags reserved tot_pdu_len 3crcrem 4 cbuff_len fw stat bfr1 bfr0 5cbuff_pntr 6 bom_bd_pntr rsvd 7 curr_bd_pntr rsvd cbfr1 8 seg_vcc_index serv_dis 9 reserved ers_index rx_counter/vpc_index 10 d_en_ncr acr_not_er d_ncr_trig d_ncr_dir reserved cong_id en_exp_cng en_imp_cng exp_ta_ci exp_ta_ni exp_ta_er 11 rsvd d_ncr_hi_exp d_ncr_hi_mant rsvd d_ncr_lo_exp d_ncr_lo_mant cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-41 table 5-11. reassembly vcc table entry format ? aal0 word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vc_en aal_type dpri reserved pass_oam aalx_en ff_dsc to_index pm_index aal_en 1 to_last to_en cur_tocnt er_efci reserved abr_ctrl 2 pdu_flags reserved tot_pdu_len 3 ccount tcount 4 cbuff_len fw stat bfr1 bfr0 5cbuff_pntr 6 bom_bd_pntr rsvd 7 curr_bd_pntr rsvd cbfr1 8 seg_vcc_index serv_dis 9 reserved ers_index rx_counter/vpc_index 10 d_en_ncr acr_not_er d_ncr_trig d_ncr_dir reserved cong_id en_exp_cng en_imp_cng exp_ta_ci exp_ta_ni exp_ta_er 11 rsvd d_ncr_hi_exp d_ncr_hi_mant rsvd d_ncr_lo_exp d_ncr_lo_mant 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-42 mindspeed technologies ? 28236-DSH-001-B table 5-12. reassembly vcc table entry format ? aal3/4 word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vc_en aal_type dpri reserved pass_oam reserved ff_dsc to_index pm_index aal_en 1 to_last to_en cur_tocnt er_efci reserved abr_ctrl 2 pdu_flags reserved tot_pdu_len 3basizersvd next_st next_sn btag 4 reserved rsvd stat bfr1 bfr0 5cbuff_pntr 6 bom_bd_pntr rsvd 7 curr_bd_pntr rsvd cbfr1 8 seg_vcc_index serv_dis 9 reserved rx_counter/vpc_index 10 reserved reserved 11 reserved reserved cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-43 table 5-13 details the descriptions of the reassembly vcc table fields. table 5-13. reassembly vcc table descriptions (1 of 3) field name description/function vc_en enables the vcc table entry. if disabled, the cell is discarded. aal_type when vc_en is a logic high, configure channel to process specific aa as listed below; otherwise, when vc_en is a logic low, a value of 11 causes the cell_dsc_cnt counter not to be incremented. 00 = aal5 01 = aal0 10 = aal3/4 11 = reserved dpri discard priority value. compared against global priority in clp and frame relay discard modes to determine discard eligibility. in lane-lecid echo suppression mode, this field is the index into the lecid table that holds channel lecid values. pass_oam when bit is set oam cells are processed and data cells are discarded without incrementing any discard counters. aalx_en when set, enables the aalx function. ff_dsc fifo buffer full discard. when a logic high, cells are discarded when the incoming dma fifo buffer is almost full. this includes oam cells when rsm_ctrl1(oam_qu_en) is a logic low. to_index selects one of eight init_tocnt values in internal sram. pm_index pointer to a pm oam processing word. index with reference to top of vpi index table. aal_en enable various cell processes. the aal_en field contains the following control bits: pm_en = enable pm oam processing on this channel. fifo_en = enable logical fifo buffer mode. lnk_en = enable writing of buffer descriptor next field. fw_en = enable firewall processing. used in conjunction with fwall_en bit in rsm_ctr0. m52_en = if set high, all 52 octets of the cell are written to a cell buffer. bintr = enable interrupt after bom buffer filled in message mode. stm_mode = enable streaming mode. lecid_en = enable lane-lecid echo suppression. invalid in aal3/4. frd_en = enable frame relay de (discard eligibility) mode. invalid in aal3/4. clpd_en = enable clp discard mode. invalid in aal3/4. to_last indicates the last vcc table entry to process for time-out. to_en enable time-out processing on the channel. cur_tocnt current time-out counter for the channel. er_efci er efci bit of the previous data cell. lnk_en fw_en m52_en bintr stm_mode lecid_en frd_en clpd_en fifo_en pm_en 98 7 6 54 3 210 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-44 mindspeed technologies ? 28236-DSH-001-B abr_ctrl set various control bits related to qfc. the qfc_ctrl field contains the following control bits: er_en = enable er operation. abr_vpc = indicates er connection is vpc (0 indicates vcc). for vpc operation, all vcc entries in the vpc group except vci=6, must be initialized with vpc_index pointing to the vcc entry corresponding with vci=6. the vci=6 entry contains the integrated efci bit over the vpc group. also, all entries in the vpc group including vci=6 must set the abr_vpc bit to a logic high. pdu_flags set various flags related to pdus. the pdu_flags field contains the following control bits: cnt_rovr = indication that service_cnt counters have rolled over. the next status entry indicates this condition. sfpd_pnd = status full packet discard pending. set when status queue is full, and cpcs must be discarded when status entries available. epd = early packet discard flag. set when epd occurs on a channel. cleared when new packet starts and error condition cleared. ci = congestion indication. pti[1] header bit ored across the cpcs-pdu. clp = cell loss priority. clp header bit ored across the cpcs-pdu. bfr_local = buffer local. if high, the current cell buffer is located in local memory; otherwise, host memory. sar maintains this bit. bd_local = buffer descriptor local. if high, the buffer descriptors reside in local memory; otherwise, host memory. sar maintains this bit. act_pdu = active pdu. indication that at least one buffer has been taken off of the free buffer queue for the current pdu being received. bom_buf = bom buffer flag. set high when filling the first buffer of a pdu. ffpd_pnd = dma fifo buffer full packet discard pending. tot_pdu_len total pdu length in bytes. crcrem cycle redundancy check remainder. crc32 remainder used in aal5 only. cbuff_len current buffer length. unused space of the current buffer in bytes. fw firewall condition. indicates that a firewall condition has occurred. ccount termination cell count. used in aal0 to terminate packet. when pti termination mode is enabled, the maximum total length of a cpcs-pdu is ccount 2 bytes. in fixed length mode, initialize to 1. tcount termination count. used in aal0 to determine the number of cells in a packet. if this field is 0 in aal0 mode, pti termination mode is enabled. basize aal3/4 basize field. used to record the basize field from the aal3/4 pdu, in order to check against the length field in the aal3/4 pdu trailer. next_st next segment type expected. next_sn next sequence number expected. btag records the aal3/4 cpcs-pdu ? s btag field, in order to check against the etag field in the cpcs-pdu trailer. stat status queue pool number. table 5-13. reassembly vcc table descriptions (2 of 3) field name description/function er_en reserved abr_vpc reserved reserved reserved reserved 65 4210 3 cnt_rovr sfpd_pnd epd ci clp bfr_local bd_local bom_buf act_pdu ffpd_pnd 31 30 29 28 27 26 24 25 23 22 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-45 bfr1 com free buffer queue pool number. bfr0 bom free buffer queue pool number. cbuff_pntr current buffer pointer. pointer to the current unused position of the cell buffer where cell payload data may be written. in logical fifo mode, the address of the fifo. bom_bd_pntr bom buffer descriptor pointer. pointer to the bom buffer descriptor. curr_bd_pntr current buffer descriptor pointer. pointer to the buffer descriptor corresponding to the current buffer in use. cbfr1 current bfr1 indication. a logic high indicates that current buffer is from bfr1 pool and logic low indicates from bfr0 pool. seg_vcc_index channel index of corresponding segmentation channel. used by er and pm-oam processing. serv_dis service discard counter. counts the number of cpcs-pdus discarded due to either lane_lecid echo suppression, clp discard, or frame relay de discard. ers_index index into er_shift table for implicit congestion er reduction. base table address is given by er_shift_b register field. rx_counter/ vpc_index when abr_vpc is a logic low, rx_counter is the firewall mode credit counter. when abr_vpc is a logic high, vpc_index is used to control a vpc group. see abr_vpc for description of this field. d_en_ncr enable destination acr/er change notification processing. acr_not_er logic high results in cr change notification; logic low results in er change notification. d_ncr_trig destination acr/er change has been triggered. initialize to logic low. d_ncr_dir indicates direction of destination acr/er trigger, logic high for hi, logic low for lo. cong_id congestion identification number. en_exp_cng enables explicit congestion er reduction mechanism. en_imp_cng enables implicit congestion er reduction mechanism; not valid when en_exp_cng is logic high. exp_ta_ci set ci to logic high in turned-around bck rm cells. exp_ta_ni set ni to logic high in turned-around bck rm cells. exp_ta_er set er to minimum of this value and in coming fwd rm er value in turned-around bck rm cells when en_exp_cng is logic high. d_ncr_hi_exp destination acr/er upper threshold, exponent portion. d_ncr_hi_mant destination acr/er upper threshold, mantissa portion. d_ncr_lo_exp destination acr/er lower threshold, exponent portion. d_ncr_lo_mant destination acr/er lower threshold, mantissa portion. table 5-13. reassembly vcc table descriptions (3 of 3) field name description/function 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-46 mindspeed technologies ? 28236-DSH-001-B 5.7.2.2 aal3/4 head vcc table entry table 5-14 shows the aal3/4 head vcc table structure. table 5-15 details the aal3/4 head vcc table field definitions. table 5-14. aal3/4 head vcc table entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vc_en aal_type reserved ff_dsc reserved pm_index aal_en 1 to_last to_en reserved mid0 mid_bits crc10_en li_en st_en sn_en cpi_en bat_en bah_en reserved er_efci reserved abr_ctrl 2 reserved vcc_index_base 3 reserved 4 reserved rsvd stat bfr1 bfr0 5 crc10_err mid_err 6li_err sn_err 7 bom_ssm_err eom_err 8 seg_vcc_index reserved 9 reserved ers_index rx_counter/vpc_index 10 d_en_ncr acr_not_er d_ncr_trig d_ncr_dir reserved cong_id en_exp_cng en_imp_cng exp_ta_ci exp_ta_ni exp_ta_er 11 rsvd d_ncr_hi_exp d_ncr_hi_mant rsvd d_ncr_lo_exp d_ncr_lo_mant table 5-15. aal3/4 head vcc table descriptions (1 of 3) field name description/function vc_en enables the vcc table entry. if disabled, the cell is discarded. aal_type when vc_en is a logic high, configure channel to process specific aal as listed below; otherwise, when vc_en is a logic low, a value of 11 causes the cell_dsc_cnt counter not to be incremented. 00 = aal5 01 = aal0 10 = aal3/4 11 = reserved ff_dsc fifo buffer full discard. when a logic high and rsm_ctrl1(oam_qu_en) is a logic low, oam cells are discarded when the incoming dma fifo buffer is almost full. pm_index pointer to a pm-oam processing word. index with reference to top of vpi index table. used by the oam cells detected on aal3/4 channels. aal_en same as aal_en field in standard rsm vcc entry. used by oam cells detected on aal3/4 channels. to_last indicates the last entry in the vcc table in which time-out processing occurs. to_en enable time-out process of the vcc entry. must be set to a logic 0. mid0 when logic high, allow a mid value of 0; otherwise, 0 is invalid. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-47 mid_bits number of significant bits for mid field. defines the limit of mid values allowed for the aal3/4 virtual connection. if the mid_bits subfield is non-0 and the aal_type is aal3/4, cpcs_mid multiplexing processing is enabled. a mid of 0 is valid only if mid0 is a logic high. mid_bits is decoded as follows: crc10_en if set high, enable aal3/4 crc10 field checking and error counting. li_en if set high, enable aal3/4 li field checking and error counting. st_en if set high, enable aal3/4 st field checking and error counting. sn_en if set high, enable aal3/4 sn field checking and error counting. cpi_en if set high, enable aal3/4 cpi field checking. bat_en if set high, enable aal3/4 basize length checking. if low, length > basize check is performed. bah_en if set high, enable aal3/4 basize < 37 checking. er_efci er efci bit of the previous data cell. vcc_index_base pointer to the first vcc table entry for this vcc with mid value = 0. all multiplexed mids on this channel are contained in a contiguous block of vcc table entries. stat status queue pool number. table 5-15. aal3/4 head vcc table descriptions (2 of 3) field name description/function mid_bits range of mid values 0000 mid processing disabled 0001 0 / 1-1 0010 0 / 1-3 0011 0 / 1-7 0100 0 / 1-15 0101 0 / 1-31 0110 0 / 1-63 0111 0 / 1-127 1000 0 / 1-255 1001 0 / 1-511 1010 0 / 1-1023 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-48 mindspeed technologies ? 28236-DSH-001-B bfr1 com free buffer queue pool number. bfr0 bom free buffer queue pool number. crc10_err number of aal3/4 cells received with crc10 error. mid_err number of aal3/4 cells received that did not have an active mid as determined by the mid_bits and mid0 fields. li_err number of aal3/4 cells received that had an unexpected li value. sn_err number of aal3/4 cells received that had an unexpected sn value. bom_ssm_err number of unexpected aal3/4 bom or ssm cells received. eom_err number of unexpected aal3/4 eom cells received. seg_vcc_index channel index of corresponding segmentation channel. used by er and pm-oam processing. ers_index index into er_shift table for implicit congestion er reduction. base table address is given by er_shift_b register field. rx_counter/ vpc_index when abr_vpc is a logic low, rx_counter is the firewall mode credit counter. when abr_vpc is a logic high, vpc_index is used to control a vpc group. see abr_vpc for description of this field. d_en_ncr enable destination acr/er change notification processing. acr_not_er logic high results in cr change notification; logic low results in er change notification. d_ncr_trig destination acr/er change has been triggered. initialize to logic low. d_ncr_dir indicates direction of destination acr/er trigger, logic high for hi, logic low for lo. cong_id congestion identification number. en_exp_cng enables explicit congestion er reduction mechanism. en_imp_cng enables implicit congestion er reduction mechanism; not valid when en_exp_cng is logic high. exp_ta_ci set ci to logic high in turned-around bck rm cells. exp_ta_ni set ni to logic high in turned-around bck rm cells. exp_ta_er set er to minimum of this value and in coming fwd rm er value in turned-around bck rm cells when en_exp_cng is logic high. d_ncr_hi_exp destination acr/er upper threshold, exponent portion. d_ncr_hi_mant destination acr/er upper threshold, mantissa portion. d_ncr_lo_exp destination acr/er lower threshold, exponent portion. d_ncr_lo_mant destination acr/er lower threshold, mantissa portion. table 5-15. aal3/4 head vcc table descriptions (3 of 3) field name description/function cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-49 5.7.3 reassembly buffer descriptor structure reassembly buffer descriptors reside on word-aligned addresses in host memory. the host controls the allocation and management of reassembly buffer descriptors. during initialization in each buffer descriptor entry, the host writes a pointer to an associated reassembly data buffer, in the buff_ptr field. table 5-16 and table 5-17 describe the format of the reassembly buffer descriptors. 5.7.4 free buffer queues the host initializes the free buffer queues in sar-shared memory, and during reassembly processing, submits data buffers for reassembly to the free buffer queues. the free buffer queue base table is located in cn8236 internal memory. table 5-18 and table 5-19 describe the format of the free buffer queue base table entries. table 5-16. reassembly buffer descriptor structure word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 next_ptr 1 buff_ptr table 5-17. reassembly buffer descriptor structure definitions field name description/function next_ptr pointer to the address of the next buffer descriptor. buff_ptr pointer to the address of the data cell buffer. note(s): the sar does not access this word; the user can place it anywhere in the buffer descriptor. table 5-18. free buffer queue base table entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved update empt bfr_local rsvd read 1length reserved bd_local rsvd forward 2 read_ud_pntr rsvd 3 reserved 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-50 mindspeed technologies ? 28236-DSH-001-B table 5-20 and table 5-21 describe the format of the free buffer queue entries. table 5-19. free buffer queue base table entry descriptions field name description/function update read index pointer update interval counter. empt free buffer queue empty flag. used to indicate that an appropriate status entry has been written to indicate the empty condition. bfr_local if logic high, cell buffers located in sar-shared memory, otherwise in host memory. read current read index pointer. length length in bytes of buffers in queue. even though length is in bytes, the user must set the length to a mod-32 bit boundary. bd_local if logic high, buffer descriptor and read_ud word are located in sar-shared memory, otherwise in host memory. forward current forward processing read index pointer (firewalling). read_ud_pntr word address in user memory to write read pointer every update interval. table 5-20. free buffer queue entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 buffer_pntr 1bd_pntr rsvd vld 2 (1) reserved reserved fwd_vld vcc_index 3 (1) (not used) note(s): (1) these words are used only in bank 0 if rsm_fbqctl(fbq0_rtn) = 1. table 5-21. free buffer queue entry descriptions field name description/function buffer_pntr pointer to beginning of cell buffer. bd_pntr pointer to corresponding cell buffer descriptor. vld free buffer valid bit. if high, location has a valid free buffer. reserved always set to 0. fwd_vld forward valid. if logic high, word contains valid buffer return information. vcc_index channel of corresponding buffer return. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-51 5.7.5 reassembly status queues the cn8236 reports reassembly status to the host on any one of 32 reassembly status queues. at initialization, the host assigns the location and size of up to 32 rsm status queues by initializing the reassembly status queue base table entries in cn8236 internal memory. the location and size of each rsm status queue is independently programmable via these base table entries. table 5-22 and table 5-23 describe the format of the reassembly status queue base table entries. table 5-24 through table 5-31 describe the formats of the reassembly status queue entries. table 5-22. reassembly status queue base table entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 base_pntr rsvd local 1 size rsvd write reserved read_ud table 5-23. reassembly status queue base table entry descriptions field name description/function base_pntr base pointer. pointer to the base word address of the status queue. local if set high, queue is located in local memory, otherwise it is located in host memory. size size of the status queue. 00 = 64 01 = 256 10 = 1,024 11 = 4,096 write current write index pointer maintained by the sar. read_ud periodic read update index pointer maintained by the user. table 5-24. reassembly status queue entry format with fwd_pm = 0 word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0bd_pntr00 1 uu cpi cpcs_length 2 rsvd pdu_checks vcc_index 3 vld reserved reserved status fwd_pm oam stm 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-52 mindspeed technologies ? 28236-DSH-001-B table 5-25. reassembly status queue entry format with fwd_pm = 1 word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0bd_pntr00 1trcc0 trcc0+1 2 rsvd pdu_checks vcc_index 3 vld reserved bipv ovfl cnt_rovr fwd_pm oam stm note(s): ovfl and cnt_rovr are defined in table 5-31 under ? status. ? table 5-26. reassembly status queue entry format with fwd_pm = 0 and aal34 = 1 word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0bd_pntr00 1 head_vcc_index cpcs_length 2 rsvd pdu_checks vcc_index 3 vld reserved aal34 reserved status fwd_pm oam stm table 5-27. pdu_checks field bits bit 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_error ba_error al_error len_error pad_error cpi_error tag_error crc_error st_error sn_error li_error lp ci_last ci table 5-28. pdu_checks field bits with cnt_rovr = 1 and aal34 = 1 bit 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_error ba_error al_error len_error pad_error cpi_error tag_error crc_error st_epd sn_epd li_epd a3l2_err table 5-29. status field bits bit 16 15 14 13 12 11 10 9 8 ffpd epd fw undf ovfl sfpd to abort cnt_rovr table 5-30. stm field bits bit 3 2 1 0 eom bom stm_mode bfr1 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-53 table 5-31. reassembly status queue entry descriptions (1 of 2) field name description/function bd_pntr buffer descriptor pointer. in message mode, pointer to the first buffer descriptor in the linked list. in streaming mode, pointer to an individual buffer descriptor. uu aal5 cpcs-uu field. cpi aal5 cpcs-cpi field. in aal0 pti terminated mode, the least significant bit contains the most significant bit of the total pdu length. the cpcs_length field contains the 16 least significant bits. cpcs_length aal5 cpcs-length field. in aal0 pti terminated mode, it is the 16 least significant bits of the total pdu length. the cpi field contains the most significant bit. trcc0 pm total received cell count for clp = 0. trcc0+1 pm total received cell count for clp = 0+1. head_vcc_index aal3/4 head vcc table entry index. when cnt_rovr = 1, aal34 = 1, and fwd_pm = 0, this field along with a3l2_err in the pdu_checks field points to the mid that rolled over. this field is also active when cnt_rovr=0, aal34=1, and fwd_pm=0. pdu_checks set various error flags related to pdus. mod_error= aal3/4 cpcs-pdu is not 32-bit aligned. ba_error = aal5: indicates that the total pdu length exceeds maximum length when auu = 1. aal3/4: basize field error occurred. al_error = aal3/4 al field is not all 0s. len_error = total cpcs-pdu length exceeds maximum length and not at end of message. pad_error= pad field length is not correct. cpi_error = cpi field is not all 0. tag_error = aal3/4 btag and etag fields in the cpcs-pdu do not match. crc_error= aal5 cpcs or oam crc error. st_epd = aal3/4 segment type error; causes epd. sn_epd = aal3/4 sequence number error; causes epd. li_epd = aal3/4 sar-pdu length error; causes epd. lp = value of clp header bit ored across the cpcs-pdu. ci_last = value of the pti[1] header bit in the last cell of the cpcs-pdu. ci = value of the pti[1] header bit ored across the cpcs-pdu. a3l2_err = when cnt_rovr = 1, aal34 = 1, and fwd_pm = 0, indicates which mib counter rolled over, based on these values: 0 = mid_err 1 = crc10_err 2 = sn_err 3 = li_err 4 = eom_err 5 = bom_ssm_err vcc_index vcc index of channel. if the connection is aal3/4 and a crc10 or mid error has occurred, this index points to a valid mid entry even though mid cannot be correctly resolved due to errors. in both cases, cnt_rovr is set and the index is only used to indicate an aal3/4 connection. vld valid. indication that status entry is valid. the host must set to 0 after processing status. aal34 indication that the status entry is relative to an aal3/4 pdu. also indicates that head_vcc_index and a3l2_err fields are active. note(s): this field is only active when fwd_pm = 0. 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-54 mindspeed technologies ? 28236-DSH-001-B status sets various status bits. the status field contains the following control bits: ffpd = dma fifo buffer full packet discard. epd = early packet discard occurred. a partially reassembled cpcs-pdu has been discarded due to firewall, buffer underflow, li_epd, sn_epd, st_epd, clp discard or max pdu length exceeded. fw = firewall error condition occurred. if early packet discard occurs, epd is set. undf = free buffer queue underflow occurred. if early packet discard occurs, epd is set. ovfl = last available status queue entry. sfpd = status full packet discard occurred. epd is not set. to = reassembly time-out condition occurred on this channel. epd is not set. abort = abort function detected. epd not set. cnt_rovr = indication that the service_cnt counter has rolled over on the channel or an aal3/4 mib counter has rolled over in an aal3/4 head vcc entry. if aal3/4 mib, then the a3l2_err field is active in the pdu_checks field and indicates which aal3/4 mib counter has rolled over. fwd_pm pm-oam forward monitoring cell detected. oam a non-0 field indicates that an oam or management cell has been received as follows: 001 = f4 oam 010 = f4 oam end to end 100 = f5 oam 101 = f5 oam end to end 110 = pti = 6 111 = pti = 7 stm sets various bits related to streaming mode. the stm field contains the following control bits: eom = in streaming mode or bom interrupt mode, this bit identifies that the buffer contains an eom. bom = in streaming mode or bom interrupt mode, this bit identifies that the buffer contains a bom. in message mode with bom interrupt enabled, indicates that status entry points to only one buffer which contains a bom. stm_mode = indication that streaming mode is enabled on the channel. bfr1 = in streaming mode, indicates which free buffer queue the buffer came from. logic high indicates com(bfr1), logic low indicates bom(bfr0). bipv bip 16 violations. same as bler0+1 field in backward reporting pm-oam cell. table 5-31. reassembly status queue entry descriptions (2 of 2) field name description/function epd fw undf ovfl sfpd to abort cnt_rovr ffpd 16 15 14 13 12 11 10 9 8 eom bom stm_mode bfr1 32 10 cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-55 5.7.6 lecid table the lecid table illustrated in figure 5-19 includes up to 32 unique identifiers for lan emulation clients (lecids). the dpri field in the reassembly vcc table entry is used as the index into this table. table 5-32 and table 5-33 display the lecid table entries and field definitions. figure 5-19. lecid table, illustrated top of vpi index table dpri (table holds 32 lecids) lecidn lecidn+ lecidn+ lecidn+ (etc.) (etc.) 8236_034 table 5-32. lecid table entries word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 lecid1 lecid0 ... ... ... 1-15 lecid31 lecid30 table 5-33. lecid table field definition field name function/description lecidn lan emulation client identifier: a unique identifier for a lan emulation client (lec). the lecid table is capable of storing 32 lecids. the system designer can initialize this table to contain the lecids of lan emulation clients that are transmitting multicast frames (point-to-multipoint emulated lan traffic) on an atm network. thus, with the lecid_en bit set to a logic high on a channel, the rsm coprocessor looks for a match in the lecid table with the lecid in each received lane frame, and if a match, the frame is discarded. this implements echo suppression of superfluous multi-broadcast lane traffic on the atm network. 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-56 mindspeed technologies ? 28236-DSH-001-B 5.7.7 global time-out table this table exists in internal sram starting at address 0x1340. the values in this table should be initialized during system initialization, before reassembly processing is started. these values set the selectable hardware pdu time-out values as described in section 5.4.9 . tables 5-34 and 5-35 display the entries and field definitions for the global time-out table. table 5-34. global time-out table entry format word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 term_tocnt1 term_tocnt0 1 term_tocnt3 term_tocnt2 2 term_tocnt5 term_tocnt4 3 term_tocnt7 term_tocnt6 4 reserved to_vcc_index table 5-35. global time-out table entry descriptions field name description/function term_tocntx time-out expiration count. to_vcc_index time-out vcc_index tracking variable. cn8236 5.0 reassembly coprocessor atm servicesar plus with xbr traffic management 5.7 reassembly control and data structures 28236-DSH-001-B mindspeed technologies ? 5-57 5.7.8 reassembly internal sram memory map as indicated in table 5-36 , the reassembly internal sram is in the address range 0x1000-0x13ff. table 5-36. reassembly internal sram memory map address name description internal reassembly status queue base table registers: 0x1000-0x1007 rsm_sq_qu0 status queue 0 base table 0x1008-0x100f rsm_sq_qu1 status queue 1 base table ? ? ? 0x10f8-0x10ff rsm_sq_qu31 status queue 31 base table internal reassembly free buffer queue base table registers: 0x1100-0x110f rsm_fbq_qu0 free buffer queue 0 base table 0x1110-0x111f rsm_fbq_qu1 free buffer queue 1 base table ? ? ? 0x12f0-0x12ff rsm_fbq_qu31 free buffer queue 31 base table other internal reassembly registers: 0x1300-0x133f reserved 0x1340-0x1353 gbl_to global time-out table 0x1354-0x13ff reserved 5.0 reassembly coprocessor cn8236 5.7 reassembly control and data structures atm servicesar plus with xbr traffic management 5-58 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? 6-1 6 6.0 traffic management 6.1 overview the traffic management capabilities of atm differentiate it from other communication technologies. the cn8236 xbr traffic manager implements the complete set of atm service categories as defined in the atm forum?s traffic management (tm) 4.1 specification . these categories include cbr, real-time and non-real-time variable bit rate (rt-vbr and nrt-vbr), ubr, gbr, and abr. table 6-1 provides a list of atm attributes detailed in the tm 4.1 specification (that is, traffic parameters, qos parameters, and feedback characteristics), and identifies whether the cn8236 supports these for each service category. the shaded areas do not indicate that the service category and attribute are undefined for the sar ? they simply indicate that the tm 4.1 specification does not detail them. 6.0 traffic management cn8236 6.1 overview atm servicesar plus with xbr traffic management 6-2 mindspeed technologies ? 28236-DSH-001-B in order to supply these services, the xbr traffic manager directs the segmentation on each active vcc by controlling the segmentation coprocessor. by intelligently selecting when each vcc transmits a cell, the traffic manager guarantees that the output of the cn8236 conforms to the negotiated traffic contract. this selection process (called scheduling) executes dynamically, based upon per-vcc parameters. the xbr traffic manager consists of two primary components. the first is the dynamic cell scheduler, which provides for cbr, vbr, ubr, and gfr traffic. second, for abr service classes, is the abr flow control manager, an additional state machine, which works in conjunction with the xbr cell scheduler. table 6-1. atm service category parameters and attributes attribute atm layer service category cbr rt-vbr (1) nrt-vbr (2) ubr (3) abr gfr traffic parameters: peak cell rate (pcr) specified/supported cell delay variation tolerance (cdvt), at pcr supported sustainable cell rate (scr) supported maximum burst size (mbs) supported cell delay variation tolerance (cdvt), at scr supported minimum cell rate (mcr) supported qos parameters: peak-to-peak cell delay variation (cdv) supported max cell transfer delay (ctd) supported (4) not supported (4) cell loss ratio (clr) supported (4) not supported (4) supported (4) not supported (4) other attributes: feedback (5) supported note(s): (1) the rt-vbr service category is intended for real-time applications; that is, those requiring tightly constrained delay and dela y variation, as would be appropriate for voice and video applications. (2) the nrt-vbr service category is intended for non-real-time applications which have bursty traffic characteristics. (3) the ubr service category is intended for non-real-time applications which do not require tightly constrained delay and delay variation. examples of such applications are traditional computer communications applications, such as file transfer and e-mail. (4) this is a network parameter. the cn8236 provides counters that monitor this parameter. (5) feedback refers to the several types of control cells called resource management cells (rm cells), which are conveyed back to the source in order to control the source transmission rate in response to changing atm layer transfer characteristics. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.1 overview 28236-DSH-001-B mindspeed technologies ? 6-3 due to the complexities of abr, a dedicated state machine is required to achieve full-rate performance ? one which reacts to feedback from the network and adjusts cell transmission accordingly. this specification models abr to align with the tm 4.1 abr specification. the cn8236 supports the rate based flow control and service models specified for abr in tm 4.1 . the cn8236 also provides generic flow control. this xon/xoff protocol complements the gfc algorithm by allowing switches to significantly overallocate port bandwidth. 6.0 traffic management cn8236 6.1 overview atm servicesar plus with xbr traffic management 6-4 mindspeed technologies ? 28236-DSH-001-B 6.1.1 xbr cell scheduler the cell scheduler maintains the qos guarantees for each service category. it rate-shapes all segmentation traffic according to per-channel parameters. this provides each channel with appropriate transmission opportunities and guarantees conformance with network traffic contract policing algorithms applied to the outputs. the cell scheduler selects individual channels based upon the dynamic schedule table. schedule slots in this table can be pre-reserved for cbr services. the vps and vcs with cbr service reserve cell slots for transmission, and are intended for highly regular data sources, such as voice circuits. the cn8236 schedules all other traffic dynamically. the proprietary dynamic scheduling algorithm uses the remaining bandwidth to statistically multiplex all other service classes onto the line. the cn8236 can manage vcc traffic on either a vc or a vp level. in addition, it can schedule traffic as a cbr tunnel (or pipe), that is, several vccs assigned to a single cbr scheduling priority, with individual vccs within that tunnel scheduled based on their traffic parameters. traffic into this cbr tunnel can be of types ubr, vbr and abr. to enhance flexibility, the cn8236 supports 16 priorities of non-cbr traffic. figure 6-1 shows a high-level block diagram of the cell scheduler control flow for cbr, vbr, and ubr traffic. the cell scheduler tracks cell slots using the system clock and decides which vcc should send during each slot. this decision is based upon per-vcc parameters and the current condition of the dynamic schedule table. unlike abr, these service categories are open loop, and need no feedback from the network for run-time cell scheduling. figure 6-1. non-abr cell scheduling atm network dynamic schedule table xbr cell scheduler per-vcc parameters and priority segmentation coprocessor system clock vcc_index cbr vbr ubr gfr 8236_035 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.1 overview 28236-DSH-001-B mindspeed technologies ? 6-5 6.1.2 abr flow control manager the cn8236 implements the atm forum abr flow control algorithms, referred to in the aggregate as abr by this document. the abr service category effectively allows 0 cell loss transmission through an atm network, by regulating transmission based upon network feedback. the abr algorithms regulate the rate of each vcc independently. figure 6-2 shows a high level block diagram of the cn8236 ? s abr feedback control loop. network feedback is received by the reassembly coprocessor and routed to the abr flow control manager. this state machine processes the feedback information according to per-vcc parameters and user-programmable abr templates, both located in sar-shared memory. these templates define abr service parameters and policies for groups of vccs. once the feedback is processed, the flow control manager provides the cell scheduler with an updated rate. under the policy imposed by the template, the rate complies with the tm 4.1 source behavior specifications. until the next update, the cell scheduler uses this rate to dynamically schedule the connection. figure 6-2. abr flow control atm network abr templates abr flow control manager dynamic schedule table cell scheduler per-vcc parameters and priority segmentation coprocessor reassembly coprocessor rate update vcc_index abr cell stream rm cell feedback 8236_036 6.0 traffic management cn8236 6.1 overview atm servicesar plus with xbr traffic management 6-6 mindspeed technologies ? 28236-DSH-001-B for optimal performance, the abr flow control manager implements the abr algorithm in a hardware state machine. however, to provide flexibility against minor changes in the immature tm 4.1 specification, the state machine is programmable through mindspeed-supplied abr templates. these templates, resident in sar-shared memory, also provide a policy tuning mechanism for interoperability and performance. separate groups of vccs can be assigned to application-optimized templates according to their path through the network. application example: application-specific templates each template may have different flow control parameters. for instance, a system designer may wish to configure a vcc traversing a network with all er switches with a rate increase factor (rif) and rate decrease factor (rdf) = 1. however, a vcc traversing a network with switches doing ci/ni (binary) marking will desire an rif and rdf 1. thus, separate templates would be desired for these vccs. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-7 6.2 xbr cell scheduler functional description 6.2.1 scheduling priority 6.2.1.1 16 priority levels + cbr the cn8236 supports 16 scheduling priorities (the pri field in the seg vcc table entry), in addition to the optional cbr service category, with 15 being the highest priority, down to 0 being the lowest priority. cbr channels are assigned a priority which is in effect higher than the 16 scheduling priorities discussed here. from one to 16 of these scheduling priorities can be assigned to vbr and abr service classes. the others are shared ubr priorities. the vbr/abr priorities must be contiguous within the 16 scheduling priorities, and thus accessible by an offset pointer. the host sets the offset of the vbr/abr priorities in the vbr_offset field of seg_ctrl or sch_ctrl. 6.2.1.2 vcc priority assignment the host assigns the priority of all vccs, except cbr vccs, by setting the pri field in the segmentation vcc table entry. this priority should be set at connection setup and should not be changed dynamically. 6.2.2 dynamic schedule table 6.2.2.1 overview the xbr cell scheduler schedules traffic according to the dynamic schedule table. the table contains a programmable number of slots, determined by sch_size(tbl_size). the duration of a single slot is a programmable number of clocks cycles, set as the number of clock cycles per schedule slot, in sch_size(slot_per). the cell scheduler sequences through this table in a circular fashion to schedule cbr, vbr, and abr traffic. ubr traffic is handled as described in section 6.2.5 . by configuring the number of slots and the duration of each slot, the system designer chooses a range of available rates. this range of available rates is dictated by the rate at which a single slot is scheduled, the size of the table, and how many slots in the dynamic schedule table each channel is assigned. the scheduler clock is selected by bit 26 (use_schref) of the sch_ctrl register, as shown in table 6-2 . table 6-2. scheduler clock selection use_schref scheduler clock 0 sysclk 1 schref 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-8 mindspeed technologies ? 28236-DSH-001-B figure 6-3 represents an example of a schedule table. in this example, the system designer has chosen 100 schedule slots. the duration of each slot is a programmable number of clock cycles. the system designer can choose to schedule cells close to the full payload data rate of sts-3c at 353.2 k cells/second. at this cell rate, each cell slot takes 95 clocks with a clock frequency of 33 mhz. the scheduler begins at slot 00 and increments its position in the table every 95 clocks. after 9500 clocks, the scheduler position returns to 00. 6.2.2.2 schedule table slots the user can select from a wide range of possible schedule slot formats. the user selects a format based on system requirements. if the system needs to generate cbr traffic, the first 16 bits of each schedule table slot are reserved for a cbr slot entry. the number of distinct vbr and abr priorities required, and the enabling of cbr traffic, govern the size requirements for each slot. the use_sch_ctrl bit in the seg_ctrl register is used to turn on and turn off the mechanisms that create the 16 scheduling priorities. this maintains backward compatibility to earlier versions of the sar, where only eight scheduling priorities were used. if the use_sch_ctrl bit is asserted, the user controls the size and format of all schedule slots through the slot_depth, 4-bit vbr_offset, and tun_pri0-offset fields in the sch_ctrl register, figure 6-3. schedule table with size = 100 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 cell schedule starts @ schedule slot 00 increments postition by one entry each slot_per current cell scheduler postion 29 assigned vcc_index(es) slot index 1 or 2 words (4 or 8 octets) } schedule slot schedule table scheduler wraps back to 00 at end of table 8236_037 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-9 and the cbr_tun bit in the seg_ctrl register. if the use_sch_ctrl bit in the seg_ctrl register is not asserted, the user controls the size and format of all schedule slots through the dbl_slot, 3-bit vbr_offset, and cbr_tun fields in the seg_ctrl register. these factors, coupled with the size of the schedule table, determine the memory requirements for the schedule table. table 6-3. selection of schedule table slot size by system requirements cbr service number of vbr/abr priorities required schedule slot size cbr_tun slot_depth available vbr/abr priority levels no 16 8 words (256 bits) 0 111 0 ? 15 (1) yes 15 8 words (256 bits) 1 111 1 ? 15 (1) no 14 7 words (224 bits) 0 110 vbr_offset + 0 ? 13 yes 13 7 words (224 bits) 1 110 vbr_offset + 1 ? 13 no 12 6 words (192 bits) 0 101 vbr_offset + 0 ? 11 yes 11 6 words (192 bits) 1 101 vbr_offset + 1 ? 11 no 10 5 words (160 bits) 0 100 vbr_offset + 0 ? 9 yes 9 5 words (160 bits) 1 100 vbr_offset + 1 ? 9 no 8 4 words (128 bits) 0 011 vbr_offset + 0 ? 7 yes 7 4 words (128 bits) 1 011 vbr_offset + 1 ? 7 no 6 3 words (96 bits) 0 010 vbr_offset + 0 ? 5 yes 5 3 words (96 bits) 1 010 vbr_offset + 1 ? 5 no 4 2 words (64 bits) 0 001 (dbl_slot = 1) (2) vbr_offset + 0 ? 3 yes 3 2 words (64 bits) 1 001 (dbl_slot = 1) (2) vbr_offset + 1 ? 3 no 2 1 word (32 bits) 0 000 (dbl_slot = 0) (2) vbr_offset + 0 or 1 yes 1 1 word (32 bits) 1 000 (dbl_slot = 0) (2) vbr_offset + 1 note(s): (1) vbr_offset would be set to 0 for this mode of operation. (2) the bottom four rows of this table describe the slot size formats when use_sch_ctrl is not asserted. 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-10 mindspeed technologies ? 28236-DSH-001-B 6.2.2.3 schedule slot formats without use_sch_ctrl asserted the vcc index contents of each schedule table slot, based on the settings in the last four rows of the table above, are illustrated in figure 6-4 . the sar can assign vbr vcc index(es) to any or all of the vbr vcc_index fields in a schedule table slot. each of the vbr fields in a schedule table slot that is assigned a vbr vcc_index has a different scheduling priority (pri), one from the other. also, any of these vbr vcc_indexes assigned by the sar can be the first of a linked list of vbr vccs. vbr_offset described vbr_offset gives the offset difference in priority level between what the user or system designer wishes to assign vbr channels and what the sar assigns via the vbr schedule slot format. thus, the value of vbr_offset is the difference between the highest vbr/abr priority being actively scheduled and the largest priority of the vbr vcc_index field in the vbr scheduling slot (either one or three). for example, if the system designer assigns vbr/abr vccs to three different scheduling priorities with the highest of those priorities being 5 (that is, pri = 5), then vbr_offset = 5 - 3 = 2. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-11 figure 6-4 illustrates how these priorities are assigned to the vbr fields. figure 6-4. schedule slot formats with use_sch_ctrl not asserted cbr vcc_index vbr vcc_index (pri=vbr_offset+1) cbr vcc_index vbr vcc_index (pri=vbr_offset+1) vbr vcc_index (pri=vbr_offset+3) vbr vcc_index (pri=vbr_offset+0) vbr vcc_index (pri=vbr_offset+0) vbr vcc_index (pri=vbr_offset+2) vbr vcc_index (pri=vbr_offset+1) vbr vcc_index (pri=vbr_offset+1) vbr vcc_index (pri=vbr_offset+3) vbr vcc_index (pri=vbr_offset+2) cbr_tun = 1, dbl_slot = 0 cbr_tun = 1, dbl_slot = 1 cbr_tun = 0, dbl_slot = 0 cbr_tun = 0, dbl_slot = 1 8236_107 = user defined note(s): 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-12 mindspeed technologies ? 28236-DSH-001-B 6.2.2.4 schedule slot formats with use_sch_ctrl asserted when use_sch_ctrl is asserted, the slot_depth and vbr_offset fields in the sch_ctrl register and the cbr_tun field in the seg_ctrl register dictate the format of each schedule slot. this format is illustrated in figure 6-5 . figure 6-5. schedule slot formats with use_sch_ctrl asserted cbr vcc_index vbr/abr vcc_index (pri=vbr_offset+1) vbr/abr vcc_index (pri=vbr_offset+3) vbr/abr vcc_index (pri=vbr_offset+5) vbr/abr vcc_index (pri=15) vbr/abr vcc_index (pri=vbr_offset+2) vbr/abr vcc_index (pri=vbr_offset+4) vbr/abr vcc_index (pri=14) (1) (1) vbr/abr vcc_index (pri=vbr_offset+1) vbr/abr vcc_index (pri=vbr_offset+0) vbr/abr vcc_index (pri=vbr_offset+3) vbr/abr vcc_index (pri=vbr_offset+5) vbr/abr vcc_index (pri=15) vbr/abr vcc_index (pri=vbr_offset+2) vbr/abr vcc_index (pri=vbr_offset+4) vbr/abr vcc_index (pri=14) (1) (1) cbr_tun = 1 cbr_tun = 0 slot_depth = 000 slot_depth = 001 slot_depth = 010 slot_depth = 111 8236_108 note(s): (1) vbr_offset would be set to 0 for these schedule slot formats. = user defined cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-13 6.2.2.5 some scheduling scenarios this section discusses a few examples of scheduling priority schemes that system designers may decide to implement. these examples demonstrate the range of flexibility that the cn8236 affords system designers and network administrators. figure 6-6 illustrates how scheduling priorities are assigned in scheduling slots. in this illustration, the number of vbr/abr priorities = 3. in addition, the tunnel at pri = 5 has shared vbr traffic. cbr_tun = 1, slot_depth = 001. the highest vbr/abr scheduling priority (pri) is 5. thus, vbr_offset = 1. the vbr/abr priorities must be contiguous in order to be accessible by vbr_offset. to ensure that these priorities remain contiguous when accessed by vbr_offset, the following condition must be met: figure 6-6. one possible scheduling priority scheme with the cn8236 cbr reserved for tunnel 1 ubr1 vbr1 vbr2 abr ubr2 ubr3 reserved for tunnel 2 service/application scheduling priority high low voice ? aal1 on aal0 vccs tunnel through public atm network signalling, ilmi, pnni traffic rt-vbr ? video nrt-vbr ? frame relay/abr mcr abr>mcr ? lan data traffic high priority ubr user traffic low priority ubr user traffic tunnel through private atm network 7 6 5 4 3 2 1 0 vbr_offset = 1 (vbr/abr priority 1) (vbr/abr priority 2) (vbr/abr priority 3) 15 8 (unused) (scheduling priorities 8 thru 15 are not used in the scheme.) (ubr only) (ubr & vbr shared) 8236_038 vbr_offset (# of vbr abr priorities) 15 ? + 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-14 mindspeed technologies ? 28236-DSH-001-B 6.2.3 cbr traffic the cbr service category guarantees end-to-end bandwidth through the network. certain data sources, such as voice circuits and constrained cell delay variation (cdv), require this guarantee. cdv is a measure of the burstiness of traffic. the atm network supplies a minimum cdv for cbr channels by reserving cell transmission opportunities for the connections. the cn8236 generates cbr traffic by assigning specific slots in the schedule table to a cbr vcc. this connection always sends a single cell during its assigned slots. the system clock serves as a time reference for cbr cell generation. the systems designer programs the duration of schedule slots in clock cycles in the slot_per (slot period) field of the sch_size register. 6.2.3.1 cbr rate selection maximum rate for each cbr assigned cell slot, the cn8236 generates one cell on the specified vcc. the maximum or base rate of cbr channels is determined by the duration of a cell slot according to the equation below, where r max is the maximum rate in cells per second. slot_per must be nominally set to the number of clock cycles needed to transmit a full cell, and its minimum bound should be no less than 70. slot_per clock frequency (sysclk or schref) r max ------------------------------------------------------------------------------------------------- = application example: determining maximum rate frequency(sysclk) = 33 mhz slot_per = 93 clocks/slot r max = 354.8 k cells/second to achieve the maximum rate, the user would assign one vcc to every cell slot in the schedule table. this would prevent any other vcc from being scheduled since this channel uses all of the available slots. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-15 6.2.3.2 available rates once a maximum rate (r max ) has been selected, the size of the schedule table determines the rate granularity and minimum rate. the system designer specifies the number of table slots in sch_size(tbl_size). the available cbr rates are as follows: minimum rate the minimum rate available is therefore r max /tbl_size . assigning cbr cell slots figure 6-7 displays an example of a schedule table with slots assigned to various cbr channels, each with a different rate. in this example, tbl_size = 100 and slot_per = 93. vcc_index a occupies every tenth schedule slot; therefore, it transmits at r/10, or 35.4 k cells/second. vcc_index b occupies a slot every 25 cell slots and transmits at a rate of r/25, or 14.2 k cells/second. vcc_index c occupies only one schedule slot and therefore transmits at the minimum rate, r/tbl_size, or 3.54 k cells/second. not all cell slots have been assigned to cbr channels. during these slots, the cn8236 dynamically schedules traffic from the other service classes. however, the total bandwidth of channels a, b, and c is reserved. r max , r max (tbl_size 1) ? tbl_size, r max (tbl_size 2) ? tbl_size, ... ..., r max tbl_size ? ? ? figure 6-7. assigning cbr cell slots 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 29 vcc_index = b schedule slot schedule table a a a a a a a a a a b b b b b c 8236_039 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-16 mindspeed technologies ? 28236-DSH-001-B 6.2.3.3 cbr cell delay variation (cdv) cbr connections are sensitive to cdv. (see atm forum uni 3.1 or tm 4.1 for a complete definition of cdv.) the cn8236 ? s traffic manager minimizes cdv by basing all traffic management on the scheduler clock frequency and providing the user the ability to explicitly decide the transmit time for cbr traffic. however, no system is without some cdv. in the case of terminals using the cn8236, the dominant factor in cdv is the variation introduced between the segmentation coprocessor and the phy layer device at the transmit fifo buffer (tx_fifo). line overhead created by the framer in the phy layer device causes this variation. figure 6-8 illustrates this interface. a possible source of schedule table-dependent cdv is created when the host contracts for different cbr rates on more than one cbr channel, causing schedule slot conflicts in the schedule table. figure 6-9 illustrates an example of a linear representation of a schedule table with 100 schedule slots. cbr channel a has reserved bandwidth for a rate of 70 k cells/second, or every fifth cell slot. cbr channel b has reserved bandwidth for a rate of 88.7 k cells/second, or every fourth cell slot. in this case there is a schedule slot reservation conflict between channels a and b every 20th cell slot, and one of the channel ? s slots has to be reserved one slot later. figure 6-8. introduction of cdv at the atm/phy layer interface cell scheduler segmentation coprocessor cells are added at cbr rate cells are removed at (line rate ? line overhead) phy interface tx_fifo (1-9 cells) 8236_040 figure 6-9. schedule table with slot conflicts at different cbr rates 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 schedule table aaaaa bb bbb b 5555 44 4 44 8236_041 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-17 another possible source of schedule-table-dependent cdv occurs for certain cbr rates whose schedule slot spacings do not evenly divide the table slot size. an example of this is illustrated in figure 6-10 , where the beginning and end of a 100-slot schedule table is shown. the system designer has reserved bandwidth for cbr channel c at a rate of 32.25 k cells/second, or every ninth cell slot. when the scheduler wraps from the end of the table to the beginning of the table, the number of schedule slots between the last c channel slot at the end of the table and the first c channel slot at the beginning of the table is 10 slots, not 9. the worst-case cdv is determined by the following formula: the first term in the formula above is introduced by cbr rate matching (see section 6.2.2.4 ). the second term in the formula above is introduced by the tx_fifo itself. the fifo buffer introduces worst case cdv when one cbr cell is transmitted through an empty fifo buffer, and the next cbr cell from that channel is segmented to a full fifo buffer. the system designer programs the tx_fifo_len in the seg_ctrl register. by reducing the tx_fifo_len, the system designer reduces cdv. however, the tx_fifo also absorbs pci bus latency. to prevent pci latency from impacting line utilization, set the tx_fifo length according to the following formula: figure 6-10. cdv caused by schedule table size at certain cbr rates 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 schedule table c c cc 999 9 9 (scheduler wraps from slot 99 to slot 00.) 8236_042 cdv max 1 (cbr rate in cells sec) ? tx_fifo_len (line rate in cells sec) ? ? + ? = tx_fifo_len > 1 (worst case pci latency) (line rate in cells sec) ? ? + 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-18 mindspeed technologies ? 28236-DSH-001-B 6.2.3.4 cbr channel management the host initializes the segmentation vcc table entry of a cbr vcc. the sch_mode of the vcc must be set to 001 (cbr). thereafter, the cn8236 ignores further processing based on the sch_mode field in the vcc table entry for cbr vccs. cbr pvc provisioning once a schedule table has been created, the system assigns specific cell slots to any cbr-provisioned virtual connections (pvcs). this process takes place before the segmentation process is initiated. once segmentation has begun, the cn8236 dynamically allocates these cell slots to other channels until the data is supplied for the cbr vcc. cbr svc setup and teardown it is also possible to set up and tear down cbr-switched virtual connections (svcs) without disrupting ongoing segmentation. the user simply configures a new vcc table entry. once the vcc is initialized, the host assigns schedule slots to the vcc according to its rate. the host then submits data as with any segmentation vcc. cbr rate matching in reality, the cbr schedule rate of a channel does not exactly match the rate of its data source. to compensate for this asynchronous data source behavior, the cn8236 provides a rate-matching mechanism for use when cbr traffic is mapped to a virtual fifo buffer. (this method is needed only for virtual fifo buffers. for vccs that are not virtual fifo buffers, the cell transmission is skipped automatically if there is no data available.) for an individual cbr channel mapped to a virtual fifo buffer, the host directs the cn8236 to skip one cell transmission opportunity whenever data is unavailable. the host requests this rate matching adjustment by setting the sch_opt bit of the cbr channel. the next time the cn8236 encounters a cbr slot for this vcc, it does not transmit data on that vcc. then, the cn8236 indicates to the host that a slot has been skipped by clearing the sch_opt bit. with this method, the host effectively synchronizes the cn8236 ? s scheduled rate to the external data source rate. the host must configure the cbr vcc rate slightly higher than the actual rate of the data source. skipping cell transmission slots then compensates for the rate differential. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-19 6.2.4 vbr traffic the cn8236 cell scheduler also supports multiple priority levels for vbr traffic. the vbr service class takes advantage of the asynchronous nature of atm by reserving bandwidth for vbr channels at average cell transmission rates without hardcoding time slots, as with cbr traffic. this dynamic scheduling allows vbr traffic to be statistically multiplexed onto the atm line, resulting in better use of the shared bandwidth resources. 6.2.4.1 mapping cn8236 vbr service categories to tm 4.1 vbr service categories the atm forum tm 4.1 specification describes the different categories of vbr service in a different manner than is employed in the cn8236 device. these relationships are described in table 6-4 . 6.2.4.2 rate-shaping vs. policing the cell scheduler rate-shapes the segmentation traffic for up to 64 k connections. the outgoing cell stream for each vcc is scheduled according to the gcra algorithm. this guarantees compliance to policing algorithms applied at the network ingress point. channels can be rate-shaped as vcs or vps, according to one of three leaky bucket paradigms, set by the sch_mode bit in the channel ? s segmentation vcc table entry. 6.2.4.3 single leaky bucket the first and simplest bucket scheme is single leaky bucket. the user defines a single set of gcra parameters ? i (interval) and l (limit). i is used to control the per-vcc pcr, and l is used to control the cdvt of the outgoing cell stream. the user enables this scheme by setting the sch_mode bits to 100 (vbr1). 6.2.4.4 dual leaky bucket the user can also select, on a per-vcc basis, to apply two leaky buckets to a single connection. the user enables this scheme by setting the sch_mode bits to 101 (vbr2). when using vbr2 sch_mode, the limitation is 256 values for the i 2 and l 2 parameters. these parameters are stored as bucket table entries. (see table 6-14 , for the definition of a bucket table entry.) there is complete flexibility with regard to using these 256 values to specify scr or pcr. in vbr2, i 1 and l 1 can specify either pcr and cvdt, or scr and burst tolerance (bt), with i 2 and l 2 used to specify the parameters not assigned to i 1 and l 1. for example, to configure i 1 = pcr, l 1 = cdvt, i 2 = scr, l 2 = bt or i 1 = scr, l 1 = bt, i 2 = pcr, l 2 = cdvt table 6-4. cn8236 vbr to tm 4.1 vbr mapping cn8236 vbr tm 4.1 vbr comments vbr1 (none) tm 4.1 does not employ single leaky bucket. vbr2 vbr.1 double leaky bucket. vbr3 (or vbrc) vbr.2 /vbr.3 tm 4.1 defines two conformance standards for clp(0+1). 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-20 mindspeed technologies ? 28236-DSH-001-B 6.2.4.5 clp-based buckets the third option allows both buckets to apply to clp = 0 cells. clp = 0 means high priority cells; clp = 1 means cells are subject to discard. clp = 1 cells are scheduled from the second bucket only. therefore, the second bucket correspond to pcr. this controls the pcr of the total cell stream, but only controls the scr of clp = 0 cells. the user enables this scheme by setting the sch_mode bits to 110 (vbrc ? also called vbr3). 6.2.4.6 rate selection the i and l parameters of the gcra algorithm represent cell slots in the schedule table. therefore, the vbr channels have the same maximum rate available as the cbr channels. since vbr channels are internally scheduled by the cell scheduler based on that channel ? s i parameter, a floating point value, they are not constrained to repeat at some n integer value of r max / (tbl_size ? n ), thus, vbr channels have a much finer rate granularity. the minimum rate for vbr channels is r max / (tbl_size ? 1). 6.2.4.7 real-time vbr and cdv real-time vbr traffic should be assigned the highest scheduling priority to minimize cell delay variation. the worst-case cdv for rt-vbr traffic is calculated as 6.2.5 ubr traffic the remaining priority levels not already assigned to abr, vbr, or cbr tunnel traffic are scheduled as ubr traffic. all ubr channels within a priority are scheduled on a round-robin basis. to limit the bandwidth that a ubr priority consumes, use a cbr tunnel in that priority level. another method of limiting the bandwidth that a ubr priority consumes is described in section 6.2.8 . 6.2.6 xbr tunnels (pipes) a cbr tunnel occupies schedule table slots in the same manner as a cbr vcc. however, instead of serving one vcc, from one to four priority levels are served. the vccs within a cbr tunnel can be ubr, vbr (vbr1 or vbr2), and/or abr traffic. in the case of a ubr priority in a tunnel, the vccs of the served priority level are serviced in round-robin order. for any vbr/abr priorities in a tunnel, each vcc is shaped to its gcra parameters within the cbr tunnel. note: the format of a cbr tunnel schedule table slot is not backward- compatible with the cbr tunnel format used in the bt8233 sar. when the user establishes a cbr tunnel, the user-defined transmit bandwidth for that tunnel is reserved in the schedule table as schedule slots. the one-to-four priority levels assigned to that tunnel are named at this time, and are written to the pri3, pri2, pri1, and pri0 fields in the cbr_tun_id field for the schedule slots reserved. pri3 should specify the highest priority level for that tunnel, down to pri0 as the lowest assigned priority level for that tunnel. the scheduler services the highest priority level that has data available on that priority queue at each point a schedule slot for that tunnel becomes active. this serves as a secondary shaping of the traffic assigned to these tunnel priorities. any one priority level can be assigned to only one cbr tunnel, and must not be assigned as a priority to more than one tunnel. additionally, all priority levels used within a ((# vbr vccs at same-or-higher priority) tx_fifo_len) (line rate in cells sec) ? ? + cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-21 cbr tunnel need to be activated as a tunnel by setting the tun_ena( ) bit(s) in the sch_pri and sch_pri2 registers. sixteen tunnels can be active at once, if each of these tunnels has only one scheduling priority assigned. all can be vbr/abr tunnels. on the other hand, the system designer can establish four tunnels, each of which has four scheduling priorities assigned to it, or any combination of tunnels, which includes up to a total of 16 scheduling priorities. individual vccs are assigned to the tunnel by the host, by setting the pri field in the vcc table to the priority of the tunnel. the 3-bit pri0 field allows the entry of only priority levels 0 through 7. if the user wishes to enter a priority level higher than priority 7 in pri0, assign the difference in values as an offset, in the tun_pri0_offset field in the sch_ctrl register. if both non-tunnel and tunnel scheduling priorities exist, the host must assign the highest priority level(s) to cbr tunnel(s). application examples: tunnels figure 6-6 shows priorities five and six used as cbr tunnels for ubr and vbr traffic. the host assigns a fixed number of schedule table slots to the tunnel to reserve a fixed rate. each time an assigned slot is encountered by the cell scheduler, it selects a vcc from a round-robin queue of active vccs assigned to that priority. for example, 100 ubr vccs with pri = 6 might currently be segmenting data. each gets 1/100th of the cbr bandwidth assigned to the tunnel. tunneling enables system-level end users to purchase cbr services from a wan service provider. the purchaser can then dynamically manage the traffic within this leased cbr tunnel as cbr and/or a combination of other service categories. in this example, the user has configured the cn8236 to manage two independent tunnels. the first tunnel priority five, is through a private atm network, perhaps a corporate atm campus backbone. the other tunnel, priority six, carries traffic through a public network. this topology allows the end user to lease reserved cbr bandwidth from an administrative domain, but manage the usage of the tunnel in an arbitrary fashion. figure 6-11 illustrates a different use of cbr tunnels. in this example, the user has established 4 separate tunnels or pipes. each can have an equal 1/4 share of the bandwidth available to the port by provisioning every fourth schedule table slot to one tunnel for each of the four tunnels. in each of the tunnels, 4 priority levels are assigned. the highest priority in each tunnel is assigned to real-time vbr, the next highest priority to non-real-time vbr, the third highest priority to abr, and the lowest priority to ubr. this in effect establishes four multi-service pipes, each on equal priority to the others (since the scheduler services each of the four pipes equally). thus, the 4 rt-vbr priorities have effectively the same priority, and so on through the four levels of priority serviced in each pipe. number of vbr/abr priorities is 12. cbr_tun = 1, slot_depth = 110. highest vbr/abr scheduling priority is 15 (that is, pri = 15). thus, vbr_offset = 3. 6.0 traffic management cn8236 6.2 xbr cell scheduler functional description atm servicesar plus with xbr traffic management 6-22 mindspeed technologies ? 28236-DSH-001-B 6.2.7 guaranteed frame rate gfr is a new service category defined by the atm forum to provide an mcr qos guarantee for aal5 cpcs-pdus (or frames) not exceeding a specified frame length. this class of service is designed specifically to utilize the ubr service category. a gfr service connection is thus treated as ubr with a guaranteed mcr. the cn8236 implements gfr by scheduling or shaping the connections using both the vbr1 scheduling procedure (for the mcr rate value) and a ubr priority queue, thereby providing fair sharing for all gfr connections to excess bandwidth. the vbr1 queue priority (the pri field in the seg vcc table entry) must be set to a higher priority than the ubr queue (the gfr_pri field in the seg vcc table entry). the priority level entered in the gfr_pri field can only be one of the lower eight scheduling priorities. this establishes the condition where those gfr connections sharing the same gfr_pri would fair-share any excess bandwidth above the mcr limits. call control must not oversubscribe mcr on gfr channels and other rate-guaranteed services. the cn8236 helps guarantee mcr on a gfr channel by providing a mechanism to trigger an increase in the scheduling priority by one priority level, if the transmit rate on that channel falls below its specified mcr. this is done using the mcrlim_idx field in that vcc ? s sch_state entry in the seg vcc table entry. mcrlim_idx is an 8-bit index into a table containing 256 figure 6-11. another possible scheduling priority scheme with the cn8236 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tunnel a tunnel b tunnel c tunnel d priority levels high vbr_offset =3 low rt-vbr nrt-vbr nrt-vbr nrt-vbr nrt-vbr rt-vbr rt-vbr rt-vbr abr abr abr abr ubr ubr ubr ubr example of multi-service tunnels 8236_043 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.2 xbr cell scheduler functional description 28236-DSH-001-B mindspeed technologies ? 6-23 entries (each formatted as described in table 6-18 ), each containing mcr limit values, and each indicating a trigger point for an increase in the vcc ? s priority for that scheduled slot. to disable this priority bumping, set mcr_limit to its maximum value. the user can accomplish this by setting each of the values in the gfr mcr limit bucket table entries as follows: 1. set nonzero bits to 1. 2. set mcr_exp fields to decimal value of 31 (all-1s). 3. set mcr_man fields to decimal value of 511 (all-1s). an additional level of traffic shaping can be established on gfr-ubr priority queues by shaping to a specified pcr. (see section 6.2.8 .) 6.2.8 pcr control for priority queues the cn8236 provides an optional method of creating tunnels (that is, limiting the bandwidth of a group of channels), by allowing the user to assign a pcr to a scheduling priority queue so that the aggregate of the rates of the channels assigned to that priority queue are not be greater than the pcr assigned. this can be done for ubr, vbr, abr, and ubr-gfr traffic classes. a maximum of four of the sixteen priority queues can be shaped to a pcr less than line rate. the queues to be shaped are identified using the qpcr_enax bits in the sch_pri and sch_pri_2 registers. the associated pcr for each queue thus enabled is specified in one of the two pcr_que_intxx registers. these pcr values are stored as schedule table intervals. qpcr_int3 maps to the highest priority queue that is enabled for pcr shaping, qpcr_int2 to the next highest priority pcr shaped queue, and so on. if only one priority queue is enabled for pcr shaping, it is shaped using the qpcr_int3 value. if two priority queues are enabled for pcr shaping, qpcr_int3 and qpcr_int2 are used, and so on. 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-24 mindspeed technologies ? 28236-DSH-001-B 6.3 abr flow control manager 6.3.1 a brief overview of tm 4.1 this section briefly describes the tm 4.1 abr flow control algorithms. however, it is strongly recommended that the reader be familiar with the atm fo r u m ? s tm 4.1 specification before attempting to understand the cn8236 ? s abr implementation. 6.3.2 internal abr feedback control loop as a complete implementation of the uni atm layer, the cn8236 acts as an abr source and destination, complying with all required tm 4.1 abr behaviors. the cn8236 utilizes the dynamic rate adjustment capability of the xbr cell scheduler as the source ? s variable rate-shaper. an internal feedback mechanism supplies feedback from the received cell stream to the abr flow control manager, a special purpose state machine. this state machine translates the feedback extracted from received backward rm cells, to instructions for the xbr cell scheduler and segmentation coprocessor. it supports both binary and er flow control methods. figure 6-12 illustrates this basic concept. figure 6-12. abr service category feedback control source destination variable rate shaping bw_rm (backward_rm) ta_rm (turnaround_rm) fw_rm (forward_rm) switch congestion algorithms atm network ( 1 switches) internal congestion backpressure 8236_044 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-25 6.3.2.1 source flow control feedback figure 6-13 illustrates the feedback loop which controls the source cell stream. the cn8236 injects an in-rate cell stream (clp = 0) into the atm network for each abr vcc. network elements modify the flow control fields in the cell stream ? s forward rm cells. after a round trip through the network and destination node, these cells return to the cn8236 receive port as backward rm cells. the reassembly coprocessor processes incoming backward rm cells, and communicates with the segmentation state machines via the rsm/seg queue in sar-shared memory. upon receiving this feedback from the queue, the abr flow control manager updates fields within the sch_state portion of the segmentation vcc table entry. the xbr cell scheduler and segmentation coprocessor use these fields to generate the abr in-rate cell stream, closing the source behavior feedback loop. the sar also processes the explicit forward congestion indication (efci) bit in the data cell header(s) per the rules in tm 4.1 . figure 6-13. cn8236 abr-er feedback loop (source behavior) backward_rm segmentation reassembly cn8236 subsystem abr decision templates schedule table abr flow control manager cell scheduler segmentation coprocessor rate decision reassembly coprocessor rsm vcc table entry sar uni atm network + destination cell type decision rsm/seg queue abr cell stream seg vcc table entry sch_state 8236_045 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-26 mindspeed technologies ? 28236-DSH-001-B 6.3.2.2 destination behavior the cn8236 also responds to an incoming abr cell stream as an abr destination. the reassembly coprocessor processes received forward rm cells. it turns around this incoming information to the segmentation coprocessor via the sch_state part of the segmentation vcc table entry. the segmentation coprocessor then formats backward rm cells containing this information and inserts these turnaround rm cells into the transmit cell stream. the cn8236 also provides a mechanism for the destination host to apply backpressure to the source. the host notifies the cn8236 of internal system congestion. the cn8236 passes this information to the source via backward rm cells, to flow control the transmitting source. the sar also processes the efci bit in the data cell header(s) per the rules in tm 4.1 . this process is illustrated in figure 6-14 . 6.3.2.3 out-of-rate cells in addition to in-rate cell streams, the cn8236 can also generate out-of-rate (clp = 1) cell streams. these clp = 1 streams compliment and enhance the information flow contained in the in-rate cell streams. an example of the use of this mechanism is to send out-of-rate forward rm cells on a channel if the transmit rate on that channel has dropped below the schedule table minimum rate. this provides a mechanism to restart scheduling of an abr vcc whose rate has dropped to 0 or below the schedule table minimum rate. figure 6-14. cn8236 abr-er feedback generation (destination behavior) segmentation coprocessor seg vcc table entry sch_state reassembly coprocessor backward_rm forward_rm (backward rm cell formatting) (forward rm cell processing) turnaround information congestion backpressure host 8236_046 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-27 6.3.3 source and destination behaviors abr ? s source and destination behavior definitions are each listed in the atm fo r u m ? s tm 4.1 specification . refer to this specification for these definitions. 6.3.4 abr vcc parameters the state of each vcc is stored individually in its seg vcc table entry. the abr parameters are stored in the sch_state portion of the segmentation vcc table entry. due to the large number of abr parameters, the sch_state of abr vccs requires an additional location in the seg vcc table. 6.3.5 abr templates the abr templates reside in sar-shared memory in a region referred to as the abr instruction table. the abr instruction table contains one or more templates. individual vccs are assigned to a single template. each template supports a group of vccs. the key parameters contained in and controlled by the abr templates are pcr, initial cell rate (icr), mcr, rif, rdf, and nrm. the user can define mcr and icr from the abr templates or from fields in the sch_state portion of the seg vcc table entry for each connection, thus giving either per-template or per-connection control of mcr and icr. this choice is globally set using the adv_abr_templ bit in the seg_ctrl register. these abr templates are furnished by mindspeed, and are downloaded to the cn8236 as a complete microcoded state machine. three components constitute a complete template: a cell decision table, a rate decision table, and an exponent table. the cn8236 uses the cell decision table to select a cell type for insertion into the transmitted in-rate cell stream. the rate decision table maps abr cell stream rates to logical states. each state includes several vectors to other states, corresponding to different rates. when an event forces a rate decision, the cn8236 decides which vector to follow based on network stimulus (ci/ni), er decisions, or internal timer/counter expirations (adtf and crm). the exponent table contains parameters for a piece-wise linear mapping function. this function maps a tm 4.1 floating point rate representation (in particular, the rm cell explicit rate field) to a rate decision table index. the exponent table is indexed by the explicit rate exponent. this mapping function normalizes the er field rate to the ci/ni state-based rate decision. once normalized, a rate can be chosen based on the minimum of the two rates. 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-28 mindspeed technologies ? 28236-DSH-001-B 6.3.6 cell type decisions 6.3.6.1 in-rate cell streams since every abr connection in a network is full duplex, the cn8236 is a source and a destination for each vcc. the cn8236 multiplexes user data cells, forward rm cells, and backward rm cells into the in-rate abr cell stream. tm 4.1 source behaviors specify rules for the in-rate cell stream. figure 6-15 shows the desired result of the specification. first, the source transmits one forward rm cell. a backward rm cell follows. finally, the source sends nrm user data cells. at steady state, this sequence would be repeated with a forward rm cell marking the beginning of each sequence. unfortunately, due to the asynchronous, asymmetrical, and fluctuating characteristics of abr connections, all connections do not maintain a steady state sequence. furthermore, since it is an immature specification, the rules for cell interleaving of in-rate cell streams may be modified slightly. the cn8236 provides a programmable mechanism to comply with tm 4.1 ? s specification on cell stream interleaving. this cell type decision algorithm makes on-the-fly decisions concerning which type of cell to send, based on the current state of the connection. figure 6-16 shows a block diagram of the algorithm. the abr flow control manager chooses a cell type based on a cell decision table and the vcc state. the segmentation coprocessor then formats the appropriate cell type and sends it on the abr in-rate cell stream. note: the abr flow control manager may choose to send no cell. this occurs when the vcc has no user data to segment. figure 6-15. steady state abr-er cell stream bw_rm fw_rm fw_rm bw_rm nrm data cells note: nominally, nrm = 32 one forward_rm cell period 8236_047 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-29 since the cell decision table template resides in sar-shared memory, the user can modify it to optimize performance or react to changes in the abr specification. furthermore, multiple tables allow groups of vccs to be tuned for different network policies. 6.3.6.2 abr cell decisions the cell decision tables reside in sar-shared memory as a segment of the flow control manager ? s abr instruction table. each entry of a table is an abr cell decision block (acdb). each acdb contains sixteen cell type actions. cell type actions result in one of four decisions: send in-rate forward rm cell, send in-rate backward rm cell, send user data cell, or no action. a cell type action is chosen by a 4-bit abr cell type decision vector (acdv). the four bits of the acdv correspond to four current abr vcc conditions. initialization instructions at system initialization, the host loads one of more cell decision tables into sar-shared memory. mindspeed provides standard cell decision tables. the system designer uses either these or customized templates. to assign an abr vcc to a table, the host initializes two sch_state fields at connection setup time. the first field, cell_index, tracks the current acdb position of the vcc. source behavior #2 specifies that the first in-rate cell on a vcc is a forward rm cell. therefore, cell_index should be initialized to an acdb position which always decides to send a forward rm cell. the second field, fwd_index, provides a reset point for the in-rate cell stream sequence. whenever the cn8236 transmits an in-rate forward rm cell, it copies fwd_index to cell_index. run-time operation each time an abr cell-transmit opportunity arises, the cn8236 makes a cell decision. the sar retrieves cell_index from sch_state and chooses a cell type action location within the current acdb. table 6-5 shows the four conditions that are used to form this vector. the presence of a condition sets the vector bit to a 1. figure 6-16. cell type interleaving on abr-er cell stream abr-er cell stream data cell forward rm backward rm cell type action seg vcc state table (sch_state) cell decision table abr flow control manager none 8236_048 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-30 mindspeed technologies ? 28236-DSH-001-B the sar updates the cell_index field after each cell decision is made. if an in-rate forward rm cell is transmitted, fwd_index is copied to cell_index; otherwise, cell_index is incremented by one (cell_index++). therefore, the number of blocks in a decision table is bounded by the maximum number of cell decisions made between transmitted forward rm cells, typically nrm. table 6-5. abr cell type decision vector (acdv) bit name description 3 trm_exp time since last forward rm transmitted >= trm 2 ta_pnd ta_pnd bit set in vcc table entry 1 ta_xmit ta_xmit bit set in vcc table entry 0 run run bit set in vcc table entry application example: cell decision table for nrm = 32 figure 6-17 shows a typical cell decision table. the anchor of the table, the fwd_index acdb, is located at index 100 of the abr decision table. whenever a forward rm cell is sent, this arcb serves as the reset point for the decision state machine. when cell_index = fwd_index, a steady state abr channel transmits a backward rm cell and advances the cell_index. the diagram shows the next acdb (101) in more detail. it contains the 16 cell type actions (for example, brm = send backward rm). at the next cell transmission opportunity, the abr flow control manager state machine selects a cell type by indexing into the acdb according to the acdv. in this case, the only condition present is run = 1, so acdv = 0001b. cell type action index 1 is selected. for this acdb, cell type action 1 is data or send data cell. therefore, the cn8236 transmits a user data cell. in steady state, cell_index is incremented until it reaches acdb 131. this acdb transmits a forward rm cell under all circumstances. therefore, the cn8236 resets the cell_index for this vcc to fwd_index = 100, when it reaches this acdb. in this example, the host should initialize cell_index to 131. the cn8236 would transmit a forward rm cell, and the sequence would continue from the fwd_index. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-31 figure 6-17. cell decision table for nrm = 32 100 101 102 103 104 129 130 131 nrm = 32 7-brm 6-brm 1-data 0-none 15-frm 14-frm 9-frm 8-frm cell_index(++) abr cell decision block fwd_index abr cell type decision vector (acdv) [trm_exp, ta_pnd, ta_xmit, run] = 0001b 8236_049 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-32 mindspeed technologies ? 28236-DSH-001-B 6.3.7 rate decisions and updates 6.3.7.1 abr traffic shaping the cn8236 schedules abr vccs as a single leaky bucket gcra channel, but the rate is subject to continual adjustment. at initialization, the host assigns flow-controlled vccs i and l parameters corresponding to the negotiated icr. the cell scheduler rate-shapes the initial traffic according to these gcra parameters. this shaped cell stream includes in-rate forward and backward rm cells. when feedback from the network results in flow control rate adjustments, the abr flow control manager overwrites the i and l parameters in the sch_state of the vcc. the updated rates fall within the range of mcr and pcr, which are specified on a per-connection basis. 6.3.7.2 rate adjustment overview the cn8236 dynamically adjusts the rate of transmission for abr vccs based upon network feedback, individual vcc parameters, and the current transmission rate. the abr flow control manager uses all of these inputs to calculate the acr of the connection. this acr corresponds to i and l gcra parameters. the cn8236 updates the i and l parameters of the vcc with the new acr i and l values. the flow control manager updates the transmission rate in response to two types of events ? the reception of a backward rm cell or the transmission of a forward rm cell. the decision process is unique for each event type. note: both of these event types may occur in one cell slot. in this case, the cn8236 makes both decisions before updating acr. 6.3.7.3 backward rm cell flow control the abr rate decision table consists of many indexed entries. each of these entries is called an abr rate decision block or ardb. each ardb represents a possible transmission rate for an abr vcc. the rate of an ardb is a monotonically increasing function of the index of the block. the cn8236 tracks the state of each abr connection ? s transmission rate by storing its current ardb index in the rate_index field of the sch_state vcc structure. this rate_index uniquely identifies the current transmission rate of the vcc. figure 6-18 illustrates a block diagram of backward rm flow control. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-33 backward rm cells deliver stimulus for two flow control algorithms. the first algorithm adjusts the state of a connection by a relative rate (rr) algorithm, in response to the ci and ni bits. the second algorithm allows the network to explicitly request a transmission rate in the er rm cell field. each of these algorithms produces a candidate rate. the source must adjust its rate to be less than or equal to the lesser of these two candidates. the cn8236 computes both rate candidates by first mapping all rate parameters into rate index space. since rate indexes are a monotonically increasing function of rate, the cn8236 selects the candidate with the lowest rate index. for the rr algorithm, the conversion is embedded in the ardbs themselves. this algorithm can adjust the rate relative to the current rate. the adjusted rate relates to the current rate by a constant multiplicative decrease or additive increase. specifically, the adjusted rate increases by (rif pcr) or decreases by (rdf acr). these values are pre-calculated and used to formulate a cn8236 abr rate instruction table, avoiding real time math. each ardb contains vectors to eight other ardbs. four of these vectors are responses to the relative rate elements in backward rm cells. the cn8236 uses the ci/ni bits to choose an ardb candidate from one of these four vectors. for instance, if ci is set, the vcc must reduce its acr by (acr x rdf). the vectors in the ardb that is chosen when ci is set point to ardbs whose corresponding rates are less than [acr ? (acr x rdf)]. the cn8236 recognizes the ardb indicated by the chosen vector, as the rr rate index candidate. figure 6-19 illustrates the rr rate_index candidate selection. figure 6-18. backward_rm flow control, block diagram backward_rm abr decision abr exponent table abr rate instruction table abr flow control manager segmentation coprocessor rate decision sar uni atm network + destination rsm/seg queue abr cell stream seg vcc table entry sch_state (rate_index) templates cell scheduler reassembly coprocessor (ci, ni & er fields) 8236_050 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-34 mindspeed technologies ? 28236-DSH-001-B the cn8236 calculates the er candidate by mapping the er field from the backward rm cell into rate index space. this mapping converts the floating point er field rate representation to an absolute rate index. this mapping does not depend on the current rate of the connection. the cn8236 maps er field to rate indexes with a programmable piece-wise linear function. each piece-wise linear segment is described in the abr exponent table. again, the system designer pre-calculates this mapping function to eliminate real-time floating point math. figure 6-19. rr rate_index candidate selection connection state (rate_index) acr acr - (acr*rdf) rr index candidate ci (compliant relative rates) rr acr-(acr*rdf) acr*rdf rate 8236_051 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-35 figure 6-20 illustrates the er rate_index candidate selection. once both candidates are identified, the cn8236 selects the smaller of the two, each of which are mcr. the winning candidate then replaces the current rate_index in the vcc ? s sch_state entry. then, the cn8236 uses this rate_index to point to the corresponding appropriate rate decision block (rdb) and, as specified in tm 4.1 , updates the vcc ? s rate parameter with the rdb ? s i and l parameters. figure 6-21 provides a block diagram of this process. the reassembly coprocessor passes the ci, ni, and er fields from the rm cell to the abr flow control manager via the rsm/seg queue. the flow control manager uses the abr rate decision table and the exponent table, both programmable components of an er template, to calculate the two rate_index candidates, each of which are mcr. the min() function is applied to select a winning candidate. then the cn8236 updates the vcc ? s rate parameters with the newly selected rate index. this rate index points to a rate decision block whose i and l parameters establish the new rate. the cell scheduler uses the updated rate to schedule all future traffic until the next rate update. figure 6-20. er rate_index candidate selection er er index candidate rate connection state (rate_index) 8236_052 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-36 mindspeed technologies ? 28236-DSH-001-B figure 6-21. dynamic traffic shaping from rm cell feedback backward_ rm cell ni ci er reassembly coprocessor rsm/seg queue abr traffic manager segmentation vcc table rate decision vector table traversal piece-wise linear mapping function exponent table dynamic scheduler tm4.0 abr rate-shaped traffic rate_index rr rate_index er rate_index min( ) rate_index -> new rate current rate update update vcc, er, ci, ni ci, ni er rr sch_state rate decision block i & l parameters 8236_109 note(s): the rr rate_index and er rate_index results are implicitly > or = mcr. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-37 6.3.7.4 forward rm cell transmission decisions the cn8236 also adjusts the transmission rates of an abr in-rate cell stream before sending a forward rm cell. this adjustment utilizes a rate decision vector selection process. as stated above, four of the eight ardb vectors are used for ci/ni rate adjustment. the other four are used for forward rm cell rate adjustments. instead of the ci/ni bits, the forward rm cell vector selection is based upon the adtf timer and the crm counter. these internal measures may force the connection to decrease its rate when sending an rm cell. the er for forward rm cells on any channel is set in word 18 of the vcc table entry (fwd_er). the normal value for fwd_er is pcr. when this field is initialized in the vcc table entry, it must be set to the rate specified by the exponent table entries so that the resulting selected rate is pcr. this is because when a forward rm cell is eventually received as a backward rm cell, the cn8236 maps the available cell rate (acr) to a rate specified by the exponent table. if pcr falls between two exponent table rates and fwd_er is set to pcr, the acr of the connection is limited to the lower of the two exponent table rates, thereby lowering the rate below pcr. 6.3.7.5 acr change notification an acr change notification mechanism per atm forum af-saa-0108* appendix d is implemented for both source and destination. five fields in the seg vcc table entry (s_en_ncr, s_ncr_lo, s_ncr_hi, s_ncr_trig, and s_ncr_dir) are used for source acr change notification. six fields in the rsm vcc table entry (d_en_ncr, d_ncr_lo_, d_ncr_hi, nd_cr_trig, d_ncr_dir, and acr_not_er) are used for destination acr/er change notification. x_en_ncr enables the acr change notification mechanism. x_ncr_lo is the low threshold value, and x_ncr_hi is the high threshold value. x_ncr_trig indicates that a notification has been triggered. x_ncr_dir indicates which threshold was crossed last, logic high for hi, logic low for lo. finally, acr_not_er allows the user to choose between destination acr or er change notification. a special status queue entry is written when the following conditions occur: x_ncr_lo triggers a notification when ? the new value of acr (1) is less than or equal to ncr_lo, and ? either this is the first notification or the last notification was triggered from ncr_hi. x_ncr_hi triggers a notification when ? the new value of acr (1) is greater than or equal to ncr_hi, and ? either this is the first notification or the last notification was triggered from ncr_lo. note: (1) for the destination change notification, this can be either acr or er depending on acr_not_er value. the special segmentation status queue (see section 4.3.6 ) containing the current acr value and is indicated by the ncr bit set to a logic 1. the src_not_dest bit indicates whether the notification is source- or destination-generated. in the case of a destination change notification the current er value (ta_er) is also provided. 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-38 mindspeed technologies ? 28236-DSH-001-B 6.3.7.6 rate adjustment in turnaround rm cells the system designer has various options for effecting a lowered explicit rate in turnaround rm cells. implicit er modification added to word 10 of the rsm vcc table entry and aal3/4 head vcc entry are the following: en_imp_chg, cong_id. added to word 9 is ers_index. when en_imp_cng is a logic high and a forward rm cell is received, sch_cng(cong_id) is checked. if a logic high, the er field is modified per the mapping mechanism described below and written into ta_er field of the seg vcc table entry. this mechanism provides an efficient per-connection hardware reduction of er values when turning around rm cells. the implicit er reduction mechanism uses a er_shift table and the er_hc_rate table to provide programmable scaled reduction of the er value based on the value ? s range. in addition, multiple er_shift tables and er_hc_rate tables may be used to allow different vccs to utilize different mappings to er_hc_rate table entries. for example, different mappings may be associated with various abr templates. a 6-bit index, ers_index, located the rs vcc table entry, indicates which er_shift table to use. the exponent portion of the er value is used as an index into the er_shift table. thus, there are 32 entries in each er_shift table. each entry contains two values, the first, hc_shift, specifies the mantissa shift mask, and the second hc_index, specifies the address of an entry into the er_hc_rate table. for hc_shift values larger than 9, no er_hc_rate table lookup is performed, and the er value from the incoming rm cell is written into the ta_er field in the seg vcc table. the number of rates in the er_hc_rate table for each exponent value is determined by: 2^^(9 >> hc_shift). the address of an er_hc_rate table entry is calculated as (er_shift_b << 5 + hc_index) + rm_cell mantissa [8:1] >> hc_shift. the right entry for this address is chosen, if the bit value of the rm_cells mantissa at its bit position hc_shift is zero, and the left otherwise. the new reduced rate is then the maximum index into the rate table has an offset of 4096 words to the er_shift_b base address. multiple er_hc_rate tables might be used. 2 ^^ hc_exp (1 hc_mant 512) ? + cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-39 explicit er modification added to word 10 of the rsm vcc table entry and aal3/4 head vcc entry are en_exp_cng and exp_ta_er. when ex_exp_cng is a logic high and a forward rm cell is received, the abr block compares the er value in the rm cell with exp_ta_er and writes the lower value to ta_er field of the seg vcc table entry. explicit ci and ni modification added to word 10 of the rsm vcc table entry and aal3/4 head vcc table entry are exp_ta_ci and exp_ta_ni. when exp_ta_ci is a logic high, the value of ci in the turned-around rm cell are asserted. when exp_ta_ci is a logic low the value of ci in the turnaround rm cell is as it has been; that is, it reflects the efci field of the last data cell or ? d with the ci value from the fwd rm cell. when exp_ta_ni is a logic high, the value of ni in the turned around rm cell are logic high; otherwise, the fwd rm cell value of ni is reflected in the turned around bck rm cell. figure 6-22. er reduction mapping rsm vcc entry ers_index er_shift table entry (16 bits) nz 15 12 11 0 er_shift_b er_shift table 0 er_shift table 63 er_hc_rate table entry 1 entry 0 entry 29 entry 28 entry 31 entry 30 mantissa shift entry 1 entry 0 entry 29 entry 28 entry 31 entry 30 rate entry 1 rate entry 0 rate entry n rate entry n-2 rate entry n-1 rate entry n-3 hc_shift hc_index hc_index er_hc_rate table entry (16 bits) 15 14 13 9 8 0 hc_exp (5) hc_mant (9) rs vd 8236_053 6.0 traffic management cn8236 6.3 abr flow control manager atm servicesar plus with xbr traffic management 6-40 mindspeed technologies ? 28236-DSH-001-B 6.3.7.7 optional rate adjustment due to use-it-or-lose-it behavior the use-it-or-lose-it behavior defined in tm 4.1 describes a rate adjustment for a vcc that has a high acr but is not actually using that bandwidth in transmission. in this case, the acr is lowered to the level of icr for that channel. the cn8236 ? s implementation of the tm 4.1 use-it-or-lose-it behavior allows the system designer to exactly tailor its operation. it uses a simple time-out mechanism, dictatable for each explicit rate. the designer selectively enables this function for the chosen rate(s) by setting the acr_ena bit to a logic high in each of the corresponding abr rate decision blocks. as a general guideline, this bit would only be set in those ardbs dictating rates above icr. in those ardbs which have this function enabled, the designer also specifies two other values: acr_to (the trigger time for the timeout value when the rate adjustment function activates), and acr_index (the new lower explicit rate index to be established when the use-it-or-lose-it behavior is triggered). as a general guideline, acr_to should be patterned on the acr decrease time factor (adtf), and acr_index should be patterned on the rate index for icr. during run time on those ardbs with the acr_ena bit set, the cn8236 compares rm_time (the schedule slot count at the time the last forward rm cell was generated) with acr_to. if the trigger point for the time-out has been reached, the cn8236 generates a new forward rm cell with the acr_index value as the assigned new explicit rate. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.3 abr flow control manager 28236-DSH-001-B mindspeed technologies ? 6-41 6.3.8 boundary conditions and out-of-rate rm cells 6.3.8.1 calculated rate boundaries when the system designer pre-calculates the rates for the ardb tables, those rates must fall within the two obvious upper and lower rate boundaries ? the lower rate boundary should not fall below mcr, and the upper rate boundary should not be calculated above pcr. 6.3.8.2 out-of-rate forward rm cell generation a mechanism must exist to restart scheduling of a vcc once the rate on that channel has dropped to 0, or is below the schedule table minimum rate (that is, the rate is less than one schedule slot on the schedule table). out-of-rate forward rm cell generation provides this mechanism. to globally enable out-of-rate forward rm cell generation, set sch_abrbase(oor_ena) to a logic high. the system designer can set the set_oor bit to a logic high in any abr rate decision block (ardb). this enables out-of-rate forward rm cell generation for that rate. when the actual cell rate on a channel has lowered to the point where scheduling of the vcc has halted, and set_oor at that rate = 1, the cn8236 sets the sch_oor bit in the vcc ? s sch_state to a logic high. the cn8236 then generates an out-of-rate forward rm cell on that channel. the cn8236 calculates the rate for generation of out-of-rate forward rm cells as follows: 6.3.8.3 out-of-rate backward rm cells the system designer can set the ta_oor bit to a logic high in any abr rate decision block. this enables the cn8236 sending a backward rm cell out-of-rate when there is a pending turnaround rm cell scheduled at that rate but not yet sent, and another forward rm cell is received. r (maximum scheduled rate) sysclk slot_per generated rate ? r (oor_int ? 1) (vcc_max 2 1) + ? ? + == = 6.0 traffic management cn8236 6.4 gfc flow control manager atm servicesar plus with xbr traffic management 6-42 mindspeed technologies ? 28236-DSH-001-B 6.4 gfc flow control manager 6.4.1 a brief overview of gfc generic flow control (gfc) is a one-way control mechanism which allows the network equipment to control the input from an end station, for the class(es) of traffic defined as controlled. this mechanism does not allow the end station to exert any control on traffic from the network. gfc is useful because it allows overbooking of the bandwidth on the input side of the network switch buffers. this allows a much higher degree of multiplexing than is otherwise possible, and allows the network-side costs of connections to be significantly reduced. by overbooking the input bandwidth, a high degree of sharing is possible, and the buffer system can be used by more end nodes than full bandwidth input would allow. gfc is used to coordinate access to that bandwidth when temporary conflicts occur. gfc provides a link-level, short-term, xon/xoff-type flow control mechanism that only works on the link from the end station to the first piece of network equipment. the gfc protocols are defined and described in itu recommendation i.361. 6.4.2 the cn8236 ? s implementation of gfc the cn8236 implements the gfc one-queue mode. the reassembly coprocessor provides auto configure and command detection. the segmentation coprocessor provides halt processing and per-transmit queue set_a control. it does not implement the optional queue b. once the link has been configured for gfc operation (as described in section 6.4.2.1 ), a received halt indication causes the segmentation coprocessor to halt processing of all channels, both controlled and uncontrolled. this halt condition continues until a cell is received without the halt indication. a received set_a indication increments the gfc credit counter by one. a gfc-controlled cell can be sent only when the gfc credit counter is equal to 1. transmission of a gfc-controlled cell decrements the credit counter by 1. each of the eight transmit priority queues can be configured for gfc control by setting the appropriate gfc n bit(s) in the scheduling priority (sch_pri) register. in this way the sar can segment both gfc-controlled and gfc-uncontrolled traffic simultaneously. gfc-controlled queues are active only when the gfc credit counter is equal to 1. cbr traffic is not affected by the set_a command because it is not mapped into a transmit priority queue. in addition, the segmentation coprocessor implements a credit borrow algorithm that provides better utilization of the line when receive and transmit cell streams are not synchronized. up to one credit can be borrowed. the user must control the transmitted gfc field via the header_mod and gfc_data fields in the buffer descriptor entries. for gfc-controlled channels, gfc_data = 0101; and for non-gfc-controlled-channels, gfc_data = 0001. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.4 gfc flow control manager 28236-DSH-001-B mindspeed technologies ? 6-43 6.4.2.1 configuring the link for gfc operation the following example describes a sequence of how to auto-configure a link for gfc operation after the link has been initialized: 1. host sets a software gfc initialization timer = 0. 2. disable reassembly coprocessor by setting rsm_ctrl0(rsm_en) = 0. 3. set the framer chip to pass unassigned cells. 4. enable the gfc link interrupt (gfc_link) by setting host_imask0 (en_gfc_link) = 1. 5. read host_istat0 register twice to clear it. 6. enable the reassembly coprocessor and set the gfc initialization timer to some user-assigned value. 7. upon occurrence of an interrupt and before the gfc initialization timer expires, read host_istat0. if gfc_link is a logic high, continue. if the timer expires before gfc_link is detected, do not enable the link for gfc processing. 8. set seg_ctrl(seg_gfc) to a logic high. 9. set the gfcn bit(s) in the sch_pri register to enable the appropriate priority queue(s) for gfc-controlled operation. 10. set the framer chip to generate unassigned cells with gfc field in cell headers set to the value of 0001. 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-44 mindspeed technologies ? 28236-DSH-001-B 6.5 traffic management control and status structures 6.5.1 schedule table at initialization, all words in the entire schedule table space should be written to 0xffffffff. individual schedule slot entries can then be initialized as either cbr slots or tunnel slots as needed. the two formats are displayed in table 6-6 . 6.5.2 cbr-specific structures 6.5.2.1 cbr traffic a schedule slot is dedicated to a cbr connection by formatting the cbr bit to a logic high and the cbr_tun_id field in the slot entry as illustrated in table 6-7 . 6.5.2.2 tunnel traffic a schedule slot is dedicated to a cbr tunnel by formatting the cbr bit to a logic low and the cbr_tun_id field of the slot entry as illustrated in table 6-8 . the schedule slot field descriptions are detailed in table 6-9 . table 6-6. schedule slot entry ? cbr/tunnel traffic word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 cbr cbr_tun_id (reserved for 1 vbr/abr pointer) 1-7 (1)(2) (reserved for 2 16-bit vbr/abr pointers) note(s): (1) word 1 is present only when the dbl_slot field in seg_ctrl is set and use_sch_ctrl is not asserted, meaning two words per schedule slot. (2) when use_sch_ctrl is asserted, the value of slot_depth determines how many additional words are used in each schedule slot; from 0 to 7 additional words. table 6-7. cbr_tun_id field, bit definitions ? cbr slot bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 def. 1 cbr_vcc_index (15 bits) table 6-8. cbr_tun_id field, bit definitions ? tunnel slot bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 def. 0pri3 pri2 pri1 pri0 cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-45 6.5.2.3 sch_state fields for cbr this section specifies the sch_state portion (words 7 through 9) of the segmentation vcc table entry, when sch_mode = cbr. the cbr sch_state is shown in table 6-10 , and the field descriptions are detailed in table 6-11 . table 6-9. schedule slot field descriptions ? cbr traffic field name description cbr set high to indicate a cbr slot; set low to indicate a tunnel slot. pri3 specifies the highest priority of four possible scheduling priority queues to service when a scheduling slot for this cbr tunnel becomes active. pri2 specifies the second highest priority of four possible scheduling priority queues to service when a scheduling slot for this cbr tunnel becomes active. pri1 specifies the third highest priority of four possible scheduling priority queues to service when a scheduling slot for this cbr tunnel becomes active. pri0 specifies the lowest priority of four possible scheduling priority queues to service when a scheduling slot for this cbr tunnel becomes active. cbr_vcc_index segmentation vcc index for dedicated cbr schedule slot. cbr vcc indexes range from 0x0000 to 0x7ffe. note(s): if the user wants only one priority of traffic scheduled in the cbr tunnel, assign the priority level to pri3, and make pri2 the same priority. pri1 and pri0 values are don ? t cares in this case. if two priorities are to be assigned to the tunnel, assign the higher priority to pri3 and the lower priority to pri2, making pri1 the same as pri2. pri0 is a don ? t care in this case. if three priorities are to be assigned to the tunnel, assigns the priorities by level to pri3 (highest), pri2 and pri1 (l owest), making pri0 the same as pri1. tun_pri0_offset can be used to set pri0 = pri1, as needed. table 6-10. sch_state for sch_mode = cbr word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 reserved tun_pri_3 tun_pri_2 tun_pri_1 tun_pri_0 8 reserved 9 reserved table 6-11. cbr sch_state field descriptions field name description tun_pri_3 when sch_mode is cbr and cbr_w_tun bit is set to 1, this field specifies the highest priority of four possible scheduling priority queues to service in place of the unused cbr slot. (this field is not active when cbr_w_tun = 0.) tun_pri_2 when sch_mode is cbr and cbr_w_tun bit is set to 1, this field specifies the second highest priority of four possible scheduling priority queues to service in place of the unused cbr slot. (this field is not active when cbr_w_tun = 0.) tun_pri_1 when sch_mode is cbr and cbr_w_tun bit is set to 1, this field specifies the third highest priority of four possible scheduling priority queues to service in place of the unused cbr slot. (this field is not active when cbr_w_tun = 0.) tun_pri_0 when sch_mode is cbr and cbr_w_tun bit is set to 1, this field specifies the lowest priority of four possible scheduling priority queues to service in place of the unused cbr slot. (this field is not active when cbr_w_tun = 0.) 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-46 mindspeed technologies ? 28236-DSH-001-B 6.5.3 vbr-specific structure 6.5.3.1 vbr sch_state tables 6-12 and 6-13 define the sch_state part of the segmentation vcc table entry, which consists of words seven through nine for vbr. see section 6.2.4 , for key data on i and l values. 6.5.3.2 vbr1 or vbr2 schedule state table table 6-12. sch_state for sch_mode = vbr1 or vbr2 word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 bucket2 (msb) l1_exp l1_man i1_exp i1_man 8 bucket2 (lsb) present 9 delta2_sign delta2_nz delta1_sign delta1_nz delta2_exp delta2_man delta1_exp delta1_man table 6-13. vbr1 and vbr2 sch_state field descriptions field name description bucket2 index into bucket table to give i2 and l2 for sched_mode = vbr2 & vbrc. bucket table base is given by seg_bckb register field. entries in bucket table have same format as l1_exp, l1_man, i1_exp, and i1_man. l1_exp gcra l parameter exponent for bucket 1. l1_exp must satisfy l1_exp <= min(i1_exp + 9,29). l1_exp that does not satisfy l1_exp >= i1_exp - 9 will have an effective l1 value of zero. l1_man gcra l parameter mantissa for bucket 1. bucket 1 l value is: 2 (l1_exp - 10) (1+l1_man/512). i1_exp gcra i parameter exponent for bucket 1. i1_exp must satisfy 10 <= i1_exp <= 25. i1_man gcra i parameter mantissa for bucket 1. bucket 1 i value is: 2 (i1_exp - 10) (1+i1_man/512). present current schedule table position. delta2_sign when set, indicates delta is negative for bucket 2. delta2_nz when set, indicates delta is non-zero for bucket 2. delta1_sign when set, indicates delta is negative for bucket 1. delta1_nz when set, indicates delta is non-zero for bucket 1. delta2_exp delta exponent for bucket 2. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-47 delta2_man delta mantissa for bucket 2. desired position for bucket 2 is: delta2_nz * 2 (delta2_exp - 10) (1 + delta2_man/512) + present. delta1_exp delta exponent for bucket 1. delta1_man delta mantissa for bucket 1. desired position for bucket 1 is: delta1_nz * 2 (delta1_exp - 10) (1 + delta1_man/512) + present. note(s): the gcra i value is expressed in cell slot intervals. example (i is not expressed in cells/sec.) table 6-13. vbr1 and vbr2 sch_state field descriptions field name description i 1 pcr ----------- - r max = 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-48 mindspeed technologies ? 28236-DSH-001-B 6.5.3.3 bucket table for vbr2 and vbrc the bucket table has only 256 entries. tables 6-14 and 6-15 display the entry format and field descriptions for the bucket table. table 6-14. bucket table entry word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved l2_exp l2_man i2_exp i2_man table 6-15. bucket table entry field descriptions field name description l2_exp gcra l parameter exponent for bucket 2. l2_exp must satisfy l2_exp min(i2_exp + 9 or 29). l2_exp that does not satisfy l2_exp i2_ex ? 9 has an effective l2 value of 0. l2_man gcra l parameter mantissa for bucket 2. bucket 2 l value is 2 (l2_exp - 10) (1 + l2_man / 512). i2_exp gcra i parameter exponent for bucket 2. i2_exp must satisfy 10 i2_exp 25. i2_man gcra i parameter mantissa for bucket 2. bucket 2 i value is 2 (i2_exp ? 10) (1 + i2_man / 512). cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-49 6.5.4 gfr-specific structures 6.5.4.1 gfr schedule state table table 6-16 and table 6-17 detail the sch_state structure for gfr traffic. table 6-16. sch_state for sch_mode = gfr word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 mcrlim_idx (msb) l1_exp l1_man i1_exp i1_man 8 mcrlim_idx (lsb) reserved 9 reserved reserved reserved reserved table 6-17. sch_state field descriptions for sch_mode = gfr field name description mcrlim_idx index into table of 256 mcr limit values each specifying an increase in the vcc ? s priority by 1 if the vcc ? s rate falls below mcr. the table base is located on top of the bucket2 table whose base is given by seg_bckb register field. the bucket2 table is 1 kb in length. table values are in the form of a non-0 bit, exponent, and mantissa such that mcr_limit is mcr_lim_nz 2 (mcr_lim_exp ? 10) (1 + mcr_lim_man / 512) l1_exp gcra l parameter exponent for mcr bucket. l1_exp must satisfy . li_exp that does not satisfy will have effective l1 value of 0. l1_man gcra l parameter mantissa for mcr bucket bucket 1 l value is 2 (l1_exp ? 10) (1 + l1_man / 512) i1_exp gcra i parameter exponent for mcr bucket. i1_exp must satisfy 10 i2_exp 25 i1_man gcra i parameter mantissa for mcr bucket. bucket 1 i value is 2 (i1_exp ? 10) (1 + i1_man / 512) l1_exp min i1_exp 9 or 29 + () l1_exp i1_exp 9 ? 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-50 mindspeed technologies ? 28236-DSH-001-B 6.5.4.2 gfr mcr limit bucket table the 128 words of this table contain 256 mcr limit values, two bucket table entries per word. the table base is on top of the bucket2 table. table values are in the form of a non-0 bit, exponent and mantissa such that mcr_limit is tables 6-18 and 6-19 describe the mcr limit bucket table. mcr_lim_nz 2 mcr_lim_exp 10 ? () 1 mcr_lim_man / 512 + () table 6-18. gfr mcr limit bucket table entry word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved non-0 mcr_exp mcr_man reserved nonzero mcr_exp mcr_man table 6-19. gfr mcr bucket table entry field descriptions field name description mcr_exp gfr mcr limit exponent. mcr_exp must satisfy mcr_exp 29. mcr_man gfr mcr limit mantissa. mcr limit is: nonzero 2 (mcr_exp ? 10) (1 + mcr_man / 512). vcc priority is increased by 1 when rate falls below 1/mcr limit. nonzero gfr mcr limit is non-0. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-51 6.5.5 abr-specific structures 6.5.5.1 abr schedule state table table 6-20 describes the sch_state entries in the segmentation vcc table for the abr service class. table 6-21 details the field descriptions for the abr sch_state fields. key: = values are furnished by the abr templates. table 6-20. sch_state for sch_mode = abr word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 reserved l_exp l_man i_exp i_man 8 reserved present 9 reserved mcr_lim_nz delta_sign delta_nz mcr_lim_exp mcr_lim_man delta_exp delta_man 10 en_src_ncr s_ncr_trig s_ncr_dir rsvd oor_pri dcr_stat tm_exp bck_oor fwd_oor sch_oor ta_xmit ta_pnd cell_index 11 fwd_index rm_time 12 rate_index eb_index 13 crm unack 14 rsvd s_nrc_lo_exp s_nrc_lo_mant next_oor 15 mcr_index icr_index 16 1 ta_id ta_dir ta_bn ta_ci ta_ni ta_ra d_ncr_dir rsvd ta_er 17 1 ta_ccr ta_mcr 18 fwd_id fwd_dir fwd_bn fwd_ci fwd_ni fwd_ra reserved fwd_er 19 rsvd s_ncr_hi_exp s_ncr_hi_mant fwd_mcr note(s): (1) words 16 and 17 are written directly by the rsm coprocessor (turnaround information). 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-52 mindspeed technologies ? 28236-DSH-001-B table 6-21. abr sch_state field descriptions (1 of 3) field name description l_exp gcra l parameter exponent for er rate. l_man gcra l parameter mantissa for er rate. i_exp gcra i parameter exponent for er rate. i_man gcra i parameter mantissa for er rate. present current schedule table position. mcr_lim_nz mcr limit is non-0. to disable priority bumping, mcr_limit must be set to its maximum value. thus, mcr_lim_nz must be set to 1. delta_sign delta is negative for er rate. delta_nz delta is non-0 for er rate. mcr_lim_exp mcr limit exponent. mcr_lim_exp must satisfy mcr_lim_exp 29. to disable priority bumping, mcr_limit must be set to its maximum value. thus, mcr_lim_exp must be set to a decimal value of 31 (binary all-1s). mcr_lim_man mcr limit mantissa. mcr_limit is mcr_lim_nz 2 (mcr_lim_exp ? 10) (1 + mcr_lim_man / 512) this format for calculating mcr_limit is the same as used with the gcra i parameter to calculate rates. vcc priority is increased by 1 when rate falls below 1 / mcr_lim. to disable priority bumping, mcr_limit must be set to its maximum value. thus, mcr_lim_man must be set to a decimal value of 511 (binary all-1s). delta_exp delta exponent for er rate. delta_man delta mantissa for er rate. desired position for er rate is delta_nz 2 (delta_exp ? 10) (1+delta_man / 512) + present en_src_ncr enable source acr change notification processing. s_ncr_trig source acr change has been triggered. initialize to logic flow. s_ncr_dir indicate direction of source acr trigger. 1 for hi, 1 for low. oor_pri segmentation priority for out-of-rate rm cells. dcr_stat destination acr change status to be sent. initialize to logic low. tm_exp rm_time value has expired and is no longer valid. bck_oor backward rm cell has been scheduled out-of-rate. fwd_oor forward rm cell has been scheduled out-of-rate. sch_oor vcc has halted due to low acr and has out-of-rate forward rm cells enabled. ta_xmit a backward rm cell has been transmitted after the last forward rm cell transmitted. ta_pnd a backward rm cell is waiting for transmission. cell_index er cell type decision block index for cell type decisions. the cell type decision block is located at byte address sch_abrb 128 + 8 cell_index. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-53 fwd_index er cell type decision block index for cell-type decisions after a forward rm cell is transmitted. rm_time global slot count [21:6] at time of last forward rm transmission. rate_index er rate decision block index. the rate decision block is located at byte address sch_abrb 128+32 rate_index. eb_index er exponent table index for rate index block. the exponent table is located at byte address sch_abrb 128 + eb_index 128. crm er parameter. unack number of forward rm cells transmitted since last backward rm cell received. initialize to 0. s_ncr_lo_exp source acr lower threshold, exponent portion. s_ncr_lo_mant source acr lower threshold, mantissa portion. next_oor next vcc index for linking out-of-rate rm cells. mcr_index minimum cell rate decision block index. the rate decision block is located at byte address sch_erb 128 + 32 mcr_index. icr_index initial cell rate decision block index. the rate decision block is locate at byte address sch_erb 128+32 icr_index. ta_id id field from most recent received forward rm cell. this field is written by the sar. ta_dir dir field for turnaround (backward) rm cell. this field is written by the sar. ta_bn bn field for turnaround (backward) rm cell. this field is written by the sar. ta_ci ci field for turnaround (backward) rm cell. this field is written by the sar. ta_ni ni field for turnaround (backward) rm cell. this field is written by the sar. ta_ra ra field from most recent received forward rm cell. this field is written by the sar. d_ncr_dir indicates direction of destination acr trigger. 1 for hi, 0 for low. ta_er er field for turnaround (backward) rm cell. this field is written by the sar. ta_ccr ccr field from most recent received forward rm cell. this field is written by the sar. ta_mcr mcr field from most recent received forward rm cell. this field is written by the sar. fwd_id id field for transmitted forward rm cells. this field is supplied by the user. fwd_dir dir field for transmitted forward rm cells. this field is supplied by the user. fwd_bn bn field for transmitted forward rm cells. this field is supplied by the user. fwd_ci ci field for transmitted forward rm cells. this field is supplied by the user. fwd_ni ni field for transmitted forward rm cells. this field is supplied by the user. fwd_ra ra field for transmitted forward rm cells. this field is supplied by the user. fwd_er er field for transmitted forward rm cells. this field is supplied by the user. s_ncr_hi_exp source acr upper threshold, exponent portion. s_ncr_hi_mant source acr upper threshold, mantissa portion. table 6-21. abr sch_state field descriptions (2 of 3) field name description 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-54 mindspeed technologies ? 28236-DSH-001-B fwd_mcr mcr field for transmitted forward rm cells. this field is supplied by the user. table 6-21. abr sch_state field descriptions (3 of 3) field name description cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-55 6.5.6 abr instruction tables an abr cell decision block consists of 16 cell type actions. the correct cell type action is selected with a 4-bit cell type decision vector. table 6-22. abr cell decision block (acdb) word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ct_act7 ct_act6 ct_act5 ct_act4 ct_act3 ct_act2 ct_act1 ct_act0 1 ct_act15 ct_act14 ct_act13 ct_act12 ct_act11 ct_act10 ct_act9 ct_act8 table 6-23. abr cell type actions value description 0000 reserved (no action). 0001 send data cell without reporting i_man and i_exp in status entry. 0010-1000 reserved (no action). 1001 send data cell with reporting of i_man and i_exp in status entry. 1010 send in-rate forward rm cell. 1011 send in-rate backward rm cell. 1110-1111 reserved (no action). table 6-24. abr cell type decision vector (acdv) bit name description 3 trm_exp time since last forward rm transmitted >= trm. 2 ta_pnd ta_pnd bit set in vcc table entry. 1 ta_xmit ta_xmit bit set in vcc table entry. 0 run run bit set in vcc table entry. 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-56 mindspeed technologies ? 28236-DSH-001-B table 6-25. abr rate decision block (ardb) word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 acr_en cong_en ta_oor set_oor l_exp l_man i_exp i_man 1 cong_er acr 2 acr_index acr_to 3rsvd 4 new_rate1 new_rate0 5 new_rate3 new_rate2 6 new_rate5 new_rate4 7 new_rate7 new_rate6 table 6-26. ardb field descriptions field name description acr_en acr ? use-it-or-lose-it ? behavior enabled on rate. cong_en enable congestion rate adjustment on rate. ta_oor out of rate rm cell turnaround enabled on rate. set_oor rate is below schedule table min rate. enable out-of-rate forward rm generation to restart vcc. l_exp gcra l parameter exponent for er rate. l_man gcra l parameter mantissa for er rate. i_exp gcra i parameter exponent for er rate. i_man gcra i parameter mantissa for er rate. i and l parameters are copied to vcc structure. cong_er new er for congestion. acr acr field for transmitted forward rm cell. acr_index new rate index for acr lose-it behavior triggered. the new rate decision block is located at byte address sch_erb*128 + 32*acr_index. acr_to acr lose-it behavior trigger time. new_rate7 - new_rate0 new rate indexes. the correct new rate index is selected with a 3-bit rate decision vector. the rate decision block is located at byte address sch_erb*128 + 32*new_raten. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-57 an exponent table maps an explicit rate to a rate decision block index. the table is indexed by the er exponent. figure 6-23 illustrates the linkage pattern between the components of the abr instruction tables. table 6-27. abr rate decision vector (ardv) value description 000 reserved/unused, or transmit forward rm cell, adtf not expired, crm not expired 001 transmit forward rm cell, adtf not expired, crm expired 010 reserved/unused, or transmit forward rm cell, adtf expired, crm not expired 011 reserved/unused, or transmit forward rm cell, adtf expired, crm expired 100 received backward rm cell with ci = 0, ni = 0 101 received backward rm cell with ci = 0, ni = 1 110 received backward rm cell with ci = 1, ni = 0 111 received backward rm cell with ci = 1, ni = 1 table 6-28. exponent table word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 rsvd shift0 exp_base0 ? rsvd ? ? 31 rsvd shift31 exp_base31 table 6-29. exponent table field descriptions field name description exp_base31-exp_ba se0 base rate decision block index. shift31-shift0 shift of er mantissa. rate index is exp_basen + mantissa>>shiftn. if the er nz bit is not set, the rate index is exp_base0. 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-58 mindspeed technologies ? 28236-DSH-001-B figure 6-23. abr linkage cell_index fwd_index rate_index eb_index er sch_state sch_erb acdb acdb acdb exponent table acdv exponent ardb acr_index new_raten ardb acr_index new_raten ardb acr_index new_raten ardv cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-59 6.5.7 rs_queue table 6-30. rs_queue entry ? oam-pm reporting information ready for transmission word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0000 oam_pm reserved bler seg_vcc_index 1 bck_tuc0 bck_tuc01 2 trcc0 trcc0+1 3 reserved table 6-31. rs_queue entry ? forward er rm cell received word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0100 er_fwd reserved seg_vcc_index 1 reserved table 6-32. rs_queue entry ? backward er rm cell received word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0101 er_bck reserved seg_vcc_index 1 reserved bn ci ni reserved er table 6-33. rs_queue field descriptions field name description oam_pm oam pm backward reporting information ready for transmission. bler block error result. seg_vcc_index segmentation vcc index for backward reporting oam pm cell. bck_tuc0 tuc0 field in received forward monitoring cell. written directly from forward_rm cell. bck_tuc01 tuc01 field in received forward monitoring cell. written directly from forward_rm cell trcc0 total received cell count with clp = 0. trcc0+1 total received cell count with clp = 0+1. er_fwd forward er rm cell received. seg_vcc_index segmentation vcc index for transmitted backward er rm cell. er_bck backward er rm cell received. bn backward explicit congestion notification bit from received rm cell. ci congestion indication bit from received rm cell. ni no increase bit from received rm cell. er explicit cell rate field from received rm cell. 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-60 mindspeed technologies ? 28236-DSH-001-B 6.5.8 scheduler internal sram registers note: for sar internal use only! application program should ignore these registers. scheduler sram registers are located in the address range 0x1640 ? 00x17ff. figure 6-24 shows the layout for the head and tail pointers. table 6-34 describes the memory map of these registers. figure 6-24. head and tail pointers 8236_166 head 31 16 15 0 tail table 6-34. scheduler internal sram memory map (head/tail pointers) address name description 0x1640 ? 0x1643 pri_pntr0 global priority 0. 0x1644 ? 0x1647 pri_pntr1 global priority 1. 0x1648 ? 0x164b pri_pntr2 global priority 2. 0x164c ? 0x164f pri_pntr3 global priority 3. 0x1650 ? 0x1653 pri_pntr4 global priority 4. 0x1654 ? 0x1657 pri_pntr5 global priority 5. 0x1658 ? 0x165b pri_pntr6 global priority 6. 0x165c ? 0x165f pri_pntr7 global priority 7. 0x1660 ? 0x1663 pri_pntr8 global priority 8. 0x1664 ? 0x1667 pri_pntr9 global priority 9. 0x1668 ? 0x166b pri_pntr10 global priority 10. 0x166c ? 0x166f pri_pntr11 global priority 11. 0x1670 ? 0x1673 pri_pntr12 global priority 12. 0x1674 ? 0x1677 pri_pntr13 global priority 13. 0x1678 ? 0x167b pri_pntr14 global priority 14. 0x167c ? 0x167f pri_pntr15 global priority 15. 0x1680 ? 0x17ff reserved not implemented. cn8236 6.0 traffic management atm servicesar plus with xbr traffic management 6.5 traffic management control and status structures 28236-DSH-001-B mindspeed technologies ? 6-61 6.0 traffic management cn8236 6.5 traffic management control and status structures atm servicesar plus with xbr traffic management 6-62 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? 7-1 7 7.0 oam functions 7.1 oam overview oam cells are atm layer management messages. these are generated by the host on the segmentation side of the cn8236, and are detected and either monitored or processed on the reassembly side of the cn8236. at m ? s oam capabilities differentiate it from other less robustly managed communication technologies. the cn8236 provides internal support for the detection and generation of oam traffic, including performance monitoring (pm) oam. the cn8236 supports the f4 and f5 oam flows according to itu-t recommendation i.610 . it also monitors the performance of up to 128 channels, generating pm-oam cells according to the same specification. 7.1.1 oam functions supported refer to itu-t recommendation i.610 for complete information on the structures and functions of oam cell generation, detection, and processing. table 7-1 lists the oam functions of the f4 and f5 oam flows, as defined in recommendation i.610 . table 7-1. oam functions of the atm layer oam function main application ais (alarm indication signal) reports defect indications in the forward direction. rdi (remote defect indication) reports remote defect indications in the backward direction. cc (continuity check) continuously monitors the continuity of a connection. a continuity cell is used periodically to check whether a connection is idle or has failed. loopback used for on-demand connectivity monitoring fault localization pre-service connectivity verification pm (performance monitoring) estimates performance and reports performance estimations in the backward direction. activation/deactivation activating/deactivating performance monitoring and continuity check. system management used by end-systems only. 7.0 oam functions cn8236 7.1 oam overview atm servicesar plus with xbr traffic management 7-2 mindspeed technologies ? 28236-DSH-001-B the cn8236 internally supports the following functions as described in itu-t recommendation i.610 : full performance monitoring functions (designed for estimating transmission performance on any channel, and for reporting performance estimations in the backward direction) detection of oam cells, and routing them as directed by the host generation of oam cells, as directed by the host implementation of the full range of functions in processing oam cells are done at the software level due to the low bandwidth of oam traffic (less than 1% of the bandwidth of active connections). cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.1 oam overview 28236-DSH-001-B mindspeed technologies ? 7-3 7.1.2 oam flows supported 7.1.2.1 f4 oam flow the f4 oam flow is the virtual path level, provided by oam cells dedicated to atm layer oam functions for virtual path connections (vpcs). the f4 flow is bidirectional. there are two kinds of f4 oam flows which can simultaneously exist in a vpc: end-to-end f4 flow (used for end-to-end vpc operations communications) segment f4 flow (used for communicating operations information within the bounds of one vpc link, such segment having its source and sink defined by the user) oam cells for the f4 flow have the same vpi value as the user cells of the vpc. f4 flow oam cells are identified as f4 flow cells by a pre-assigned vci value of three (segment flow cell) or four (end-to-end flow cell) as shown in table 7-2 . the same pre-assigned vci value is used for both directions of the f4 flow. 7.1.2.2 f5 oam flow the f5 oam flow is the virtual channel level, provided by oam cells dedicated to atm layer oam functions for vccs. the f5 flow is bidirectional. there are two kinds of f5 oam flows which can simultaneously exist in a vcc: end-to-end f5 flow (used for end-to-end vcc operations communications) segment f5 flow (used for communicating operations information within the bounds of one vcc link, such segment having its source and sink defined by the user) oam cells for the f5 flow have the same vpi value and vci value as the user cells of the vcc. f5 flow oam cells are identified as f5 flow cells by a pre-assigned pti code value of 100 (segment flow cell) or 101 (end-to-end flow cell) and shown in table 7-3 . the same pre-assigned pti value is used for both directions of the f5 flow. table 7-2. vci values for f4 oam flows vci value interpretation 3 segment oam f4 flow cell 4 end-to-end oam f4 flow cell table 7-3. pti values for f5 oam flows pti code interpretation 100 segment oam f5 flow cell 101 end-to-end oam f5 flow cell 7.0 oam functions cn8236 7.1 oam overview atm servicesar plus with xbr traffic management 7-4 mindspeed technologies ? 28236-DSH-001-B 7.1.2.3 performance monitoring (pm) performance monitoring includes a set of functions that monitor and process user information on a channel to produce maintenance information specific to that channel. this maintenance information is added to the in-rate data flow on that channel in the form of pm cells, added at the source of a connection or link, and extracted at the sink of a connection or link. with this maintenance information, the user can estimate and analyze the transport integrity of that channel. the pm flow is bidirectional, and pm cells are of two basic function types: forward monitoring cells (which carry the forward error detection information), and backward reporting cells (which carry the results of the performance monitoring checks). the cn8236 performs pm on up to 128 user-assigned channels. the sar enables pm for a channel by setting the pm enable bits (pm_en) in the segmentation and reassembly vcc state table entries for that channel. the cn8236 performs pm processing on any channel by monitoring blocks of user cells on that channel. the size of this block of cells is set by the user, and can have the value (n) of 128, 256, 512, or 1024 cells. the cn8236 inserts a pm cell after every n user cells on that channel. a block size of 0 is valid when the sar is a destination point only for pm processing. in this case, the segmentation coprocessor only generates backward reporting cells in response to reassembly performance monitoring calculations. pm as performed by the cn8236 calculates the following: errored blocks (by means of a bip-16 error detection code generated over the payloads of the user cells in the pm block) a count of mis-inserted pm forward monitoring cells the user can activate pm on any channel either during connection establishment, or at any time after the connection has been established. cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.1 oam overview 28236-DSH-001-B mindspeed technologies ? 7-5 7.1.3 oam cell format figure 7-1 illustrates the common oam cell format and identifies the fields specific to oam. figure 7-1. oam cell format oam cell information fields cell header oam type function type function specific fields (rsvd) edc (crc-10) header hec vpi vci pti l gfc 5 octets 2 octets 45 octets 4 bits 3 bits 8 bits 8 bits 1 bit 4 bits 4 bits 6 bits 10 bits 4 bits 8 bits 12 bits f4 flow (vp) vci 3 = segment vci 4 = end-to-end f5 flow (vc) pti 100 = segment pti 101 = end-to-end = generated by the cn8236 for all oam cells. = generated by the cn8236 for pm oam only. note(s): edc = error detection code (10 bits). this is a crc-10 error detection code computed over the oam cell information fields, excluding the edc field. 8236_110 7.0 oam functions cn8236 7.1 oam overview atm servicesar plus with xbr traffic management 7-6 mindspeed technologies ? 28236-DSH-001-B the oam type and function type identifiers as specified by i.610, are listed in table 7-4 . 7.1.4 local vs. host processing of oam atm carries with it significant network management overhead. the cn8236 supports those robust oam features described previously. due to the breadth of atm applications and the continuing evolution of atm management standards, it is essential that a range of flexibility be provided in the processing of network management overhead. to provide this flexibility, the cn8236 includes an optional local processor interface. since the cn8236 is capable of sar-shared memory segmentation and reassembly, it can route oam traffic including pm traffic to and from this local processor, thereby off-loading atm network management from the host. thus, host processing power is focused on the user applications specifically concerned with processing atm user data traffic. to accomplish this, the cn8236 provides global oam buffer and status queues (oam_bfr_qu and oam_stat_qu, addresses for both assigned in the rsm_ctrl1 register). if the oam_qu_en bit in the rsm_ctrl1 register is set to a logic high, the cn8236 routes oam traffic to these global queues. with sar-shared memory addresses assigned to these global queues, the cn8236 processes oam traffic through the local processor, thereby freeing the host from these management functions. in addition, the global oam segmentation status queue, seg_ctrl(oam_stat_id), is used if the oam_stat bit in the segmentation buffer descriptor is a logic high. table 7-4. oam type and function type identifiers oam type (1) coding function type (2) coding fault management 0001 ais rdi continuity check loopback 0000 0001 0100 1000 performance management 0010 forward monitoring backward reporting 0000 0001 activation/deactivation 1000 performance monitoring continuity check 0000 0001 note(s): (1) oam type indicates the type of management function performed by this cell (for example, fault management, performance management, etc.). (2) function type indicates the actual function performed by this cell within the management type indicated by the oam type field. cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.2 segmentation of oam cells 28236-DSH-001-B mindspeed technologies ? 7-7 7.2 segmentation of oam cells the host (or local processor) places oam cells in a single buffer, and thus allocates a single segmentation buffer descriptor (sbd) for the oam cell data buffer, not a linked list of sbds. the host (or local processor) then writes a pointer to that sbd in the next available transmit queue entry, and sets the vld bit to 1. when the segmentation coprocessor processes that transmit queue entry, it submits the oam cell data buffer to the xbr traffic manager and the cell is thus scheduled for transmission. 7.2.1 key oam-related fields for oam segmentation 7.2.1.1 segmentation buffer descriptors several fields in the sbd entry are used to facilitate segmentation of oam cells. set the 2-bit aal_opt field to single (value = 01). this enables reading 48 octets from a single buffer to form a single atm cell. set the oam_stat bit to a logic high. the cn8236 now reports status to the oam-dedicated oam_stat_id identified in the seg_ctrl register, instead of the stat specified in the seg vcc table entry. set the single-bit header_mod field to a logic 1. this activates the wr_pti and wr_vci bits in the buffer descriptor, which signal the cn8236 to overwrite the atm header pti and vci fields for that cell with the values from the pti_data and vci_data fields. in this way, f4 and f5 flow oam cells can be generated by the cn8236. the vci_data field set to a value of three (segment cell) or four (end-to-end cell) generates an f4 flow oam cell. the pti_data field set to a value of 100 (segment cell) or 101 (end-to-end cell) generates an f5 flow oam cell. set the aal_mode field to 01 (aal0). set both bom and eom bits to 0. set the crc10 bit to a logic high. 7.2.1.2 low latency transmission for low latency, the link_head bit in the transmit queue entry should be set to a logic high. this tells the cn8236 to link the buffer chain at the head of the existing chain for the corresponding vcc. this bit is intended for use with the seg buffer descriptor ? s single option, to send in-line oam cells. only a single seg buffer descriptor can be linked to a transmit queue entry when this bit is set. this bit must also be set if the oam sbd is placed on the transmit queue after a partial pdu, to ensure correct segmentation. 7.2.1.3 segmentation status queue the single bit in the seg status queue entry should be set to a logic high. this bit is set if the single option in the aal_opt field of the seg buffer descriptor is set. this bit indicates a special buffer is in use, rather than the normal system-assigned buffers for normal cpcs-pdus. 7.2.1.4 f4 flow for f4 flow operation, a separate vcc table entry must be configured. 7.0 oam functions cn8236 7.2 segmentation of oam cells atm servicesar plus with xbr traffic management 7-8 mindspeed technologies ? 28236-DSH-001-B 7.2.2 error condition during oam segmentation each oam cell has a 10-bit error detection code (edc) field, for storing and transporting the calculated crc-10 error detection code results (computed over the oam cell information fields, excluding the edc field). to enable this crc-10 function, set the crc10 bit in the seg buffer descriptor entry to a logic high. cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.3 reassembly of oam cells 28236-DSH-001-B mindspeed technologies ? 7-9 7.3 reassembly of oam cells to enable the reassembly coprocessor to detect and therefore further process oam cells, set the oam_en bit in rsm_ctrl1 to a logic high. the cn8236 detects the following oam cell flows: segment f4 flow end-to-end f4 flow segment f5 flow end-to-end f5 flow pti = 6 pti = 7 the cn8236 provides global oam buffer and status queues (oam_bfr_qu and oam_stat_qu, addresses for both assigned in the rsm_ctrl1 register). to activate these queues, set the oam_qu_en bit in the rsm_ctrl1 register to a logic high. the cn8236 then routes oam traffic to these global buffer and status queues. note: the cell buffer size must be large enough to hold a complete cell, when oam detection is enabled. 7.3.1 key oam-related fields for oam reassembly 7.3.1.1 reassembly vcc state table the reassembly vcc state table field, seg_vcc_index, should be written to point to the channel index of the corresponding segmentation channel. this is necessary for pm-oam and abr channels. 7.3.1.2 reassembly status queue the 3-bit oam field in the rsm status queue entry must be set to the value indicated in the rsm status queue structure description for that field. a non-0 value in the oam field indicates that the cell is an oam cell. if the crc-10 error detection code computation on the oam cell shows an error, the cn8236 sets the crc_error bit in the status queue entry to a logic high. 7.3.1.3 f4 flow for f4 flow operation, a separate vcc table entry must be configured. 7.0 oam functions cn8236 7.3 reassembly of oam cells atm servicesar plus with xbr traffic management 7-10 mindspeed technologies ? 28236-DSH-001-B 7.3.2 oam reassembly operation received oam traffic should be detected and routed to the global oam buffer and status queues (oam_bfr_qu and oam_stat_qu). the reassembly coprocessor treats oam cells as one-cell pdus. the rsm coprocessor transfers the 48-octet oam payload to the next available global data buffer and writes a rsm status queue entry. once an oam cell is detected, the rsm coprocessor checks the cell to determine whether it is a pm cell by seeing if the oam_type field in the cell is set to value 0010. that pm detection is only performed on f4 and f5 oam cells. if the rsm coprocessor finds the cell is a pm cell, it is processed following the guidelines described in section 7.4 . note: oam cells that get buffers from the global oam free buffer queue do not effect the per-vcc firewall calculation. 7.3.3 error conditions during oam reassembly the rsm coprocessor computes the crc-10 error detection code each received oam cell ? s information fields. if an error is detected (for example, the computed crc value does not match the crc-10 value written in the cell), the sar sets the crc_error bit in the status queue entry to a logic high. cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.4 pm processing 28236-DSH-001-B mindspeed technologies ? 7-11 7.4 pm processing oam performance monitoring can be enabled for up to 128 vccs by setting the pm_en bits in the rsm vcc table entry and the seg vcc table entry for that channel. figure 7-2 illustrates the functional blocks for pm processing. figure 7-2. functional blocks for pm segmentation and reassembly seg_pm table rsm_pm table oam_bfr_qu oam_stat_qu pm_index pm_index top of vpi index table, +64 bytes rs_queue segmentation coprocessor rsm vcc table seg vcc table reassembly coprocessor (global oam rsm buffer queue) (global oam rsm status queue) (bip-16 calculation) phy 8236_054 7.0 oam functions cn8236 7.4 pm processing atm servicesar plus with xbr traffic management 7-12 mindspeed technologies ? 28236-DSH-001-B for any channel on which pm processing is enabled, the cn8236 performs these functions: the rsm coprocessor reassembles received pm-oam cells in the global reassembly oam buffer queue (oam_bfr_qu). a reassembly status record is written to the global reassembly oam status queue for each received pm-oam cell. the status entry for a forward monitoring pm-oam cell includes the block error result (bipv) calculation, and both total received cell counts (trcc0 and trcc0+1). the two total user cell number fields (tuc0 and tuc0+1) can be extracted directly from the cell payload. the rsm coprocessor performs the bip-16 calculation on each received data cell in the defined pm block and writes this data to the rsm_pm table entry set aside for that pm_index. for each forward monitoring pm cell received, the rsm coprocessor writes an entry for a backward reporting pm cell in the rs_queue, causing the cn8236 to generate and transmit a backward reporting pm cell. the segmentation coprocessor automatically generates a forward monitoring pm cell at the end of each pm block. it gets the data for these cells from the seg_pm table entry for that pm_index. this can be optionally disabled by setting the fwd_mon field equal to 0. 7.4.1 initializing pm operation the user must initialize the fields described in table 7-5 before starting pm processing. table 7-5. pm-oam field initialization for any pm_index register / table field initialized value notes rsm_ctrl1 (reassembly control register 1) oam_en 0-1 oam_qu_en 0-1 oam_bfr_qu (user assigned) oam_stat_qu (user assigned) seg_pmbase (seg pm base register) seg_pmb[15:0] (user assigned) base address for seg_pm table. cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.4 pm processing 28236-DSH-001-B mindspeed technologies ? 7-13 7.4.2 setting up channels for pm operation when the cn8236 receives a pm activation cell (oam type = 1000, function type = 0000), or when the user decides to activate pm processing on a channel, the host (or local) processor must enable pm on the applicable channel by setting the pm_en bits in the rsm and seg vcc table entries to logic high and selecting an unused pm_index (0-127). the host then initializes the corresponding seg_pm and rsm_pm table entries. the format of each entry of the seg_pm table is illustrated in table 7-6 , while the format of each entry of the rsm_pm table is illustrated in table 7-8 . the assigned pm_index value for that channel has to be written to both the rsm vcc table entry and the seg vcc table entry for that channel. for f4 flows, each vci channel in the vpi group must have the pm_en bits in both the rsm vcc table entry and the seg vcc table entry set high, and the pm_index pointing to the same location. in addition, a rsm and seg vcc table entry must be configured corresponding to vci = 3 or vci = 4. to initialize backward reporting without forward monitoring on any channel, set fwd_mon = 0. once the seg_pm and rsm_pm table entries have been initialized, the processor sends an activation confirmed oam cell to the originator. 7.4.3 pm operation pm processing operates automatically on any channel until stopped by clearing the pm_en fields in the seg vcc table entry and the rsm vcc table entry. pm-oam cells are not included in the nrm cell count, as part of er processing. see chapter 6.0 , for details. 7.4.3.1 generation of forward monitoring pm cells the segmentation coprocessor generates a forward monitoring pm cell at the end of each pm block, as defined by the block_size field in the seg_pm table for any pm_index. it determines the point to generate a forward monitoring cell by following these processes: at the point of initialization of pm processing or when a forward monitoring cell is sent, the seg coprocessor sets the block_count field to 0. it also increments monitoring cell sequence number (msn), and re-initializes the bip field to 0. as each data cell is segmented, the seg coprocessor increments the block_count number and updates the bip field. when the block_count number reaches the block size specified by the block_size field, signifying the end of the pm block, the seg coprocessor generates a new forward monitoring pm cell and starts these processes again. 7.0 oam functions cn8236 7.4 pm processing atm servicesar plus with xbr traffic management 7-14 mindspeed technologies ? 28236-DSH-001-B 7.4.3.2 reassembly of forward monitoring pm cells when the cn8236 receives a forward monitoring pm cell, the rsm coprocessor reads the rsm_pm table word pointed to by the pm_index field in the rsm vcc table entry. the location of the rsm_pm table is above the lecid table. the bipv, trcc0, and trcc0+1 fields are written to a special rsm-pm forward monitoring status queue entry. the tuc0 and tuc0+1 fields can be extracted directly from the rsm_pm cell payload. when a new buffer is needed, the reassembly coprocessor uses the global oam buffer queue if rsm_ctrl1(oam_qu_en) is a logic high. otherwise, it uses the bfr0 pool identification number in the rsm vcc table to point to the appropriate free buffer queue. a rsm status entry is written for each oam cell reassembled. the reassembly coprocessor uses the global oam status queue if the rsm_ctrl1(oam_qu_en) bit is a logic high. otherwise, it uses the stat field in the rsm vcc table to determine which status queue to use for that channel. 7.4.3.3 reassembly of backward reporting pm cells backward reporting cells are reassembled in the same manner as non-pm oam cells. 7.4.3.4 turnaround and segmentation of backward reporting pm cells for each forward monitoring cell received, the cn8236 also writes the bipv, trcc0, trcc0+1, tuc0, and tuc0+1 fields to the rs_queue for further processing by the segmentation coprocessor. the segmentation coprocessor generates a backward reporting cell. 7.4.3.5 turnaround of backward reporting pm cells only to enable turnaround of backward reporting pm cells without generation of forward monitoring pm cells, set the segmentation pm_en bit in the seg vcc table entry to a logic high, set the pm_index, and set the fwd_mon field to 0. 7.4.4 error conditions during pm processing if oam cells are not using the global reassembly oam buffer pool, the cells are treated as single segment messages (ssms) for purposes of firewall protection. oam cells using the global oam buffer pool do not have per channel protection. if the rs_queue fills, the pm-oam information is dropped, and the rs_queue_full status indication is set. 7.4.5 pass_oam function a pass_oam only function is activated by setting bit 22 of word 0 in the rsm vcc table. when active, oam cells are processed, and data cells are discarded without incrementing any discard counters. cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.5 oam control and status structures 28236-DSH-001-B mindspeed technologies ? 7-15 7.5 oam control and status structures refer to section 4.3 and section 5.7 for information on vcc tables, buffer descriptors, the transmit queue, and status queues, as they apply to generating and processing oam cells. the base address of the seg_pm table is given by the seg_pmb field in the seg_pmbase register. the address of each entry is located at byte address, seg_pmb 128 + (pm_index) 32. the rsm_pm table is located above the lecid table, which is located above the vpi table. the address of each entry is located at byte address, if rsm_ctrl0(vpi_mask) rsm_itb 128 + 1024 + 64 + (pm_index) 16 else rsm_itb 128 + 16384 + 64 + (pm_index) 16 7.5.1 seg_pm structure tables 7-6 and 7-7 describe the structure and field definitions of the seg_pm table. table 7-6. seg_pm structure word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 atm_header 1 fwd_tuc0 fwd_tuc01 2 fwd_pm block_size fwd_mon rsvd block_count bip 3 reserved bler bck_msn fwd_msn 4 bck_tuc0 bck_tuc01 5 trcc0 trcc01 6 reserved 7 reserved 7.0 oam functions cn8236 7.5 oam control and status structures atm servicesar plus with xbr traffic management 7-16 mindspeed technologies ? 28236-DSH-001-B table 7-7. seg_pm field descriptions field name description atm_header atm header to use for both backward-reporting and forward-monitoring cells. fwd_tuc0 total user cell number with clp = 0 for forward-monitoring. fwd_tuc01 total user cell number with clp = 0, 1 for forward-monitoring. fwd_pm initialized to 0. set to 1 when block_count reaches its block_size limit, signifying that a pm cell is ready to forward. block_size size in cells of forward-monitoring block: 00: block size = 128 01: block size = 256 10: block size = 512 11: block size = 1024 fwd_mon set to enable both forward-monitoring and backward-reporting. clear to enable only backward-reporting. block_count number of cells in current monitoring block. bip bip-16 for forward-monitoring. bler block error result for backward-reporting cells. bck_msn monitoring cell sequence number for backward-reporting cells. fwd_msn monitoring cell sequence number for forward-monitoring cells. bck_tuc0 tuc0 field for backward-reporting cells. bck_tuc01 tuc01 field for backward-reporting cells. trcc0 total received cell count with clp = 0 for backward-reporting. trcc01 total received cell count with clp = 0,1 for backward-reporting. cn8236 7.0 oam functions atm servicesar plus with xbr traffic management 7.5 oam control and status structures 28236-DSH-001-B mindspeed technologies ? 7-17 7.5.2 rsm_pm table tables 7-8 and 7-9 describe the structure and definitions of the rsm_pm table. table 7-8. rsm_pm table entry word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved msn 1 bip16 bcnt 2 trcc0 trcc0+1 3 reserved table 7-9. rsm_pm table field descriptions field name description msn monitoring cell sequence number for forward-monitoring pm cells. backward-reporting pm cells are not included in this sequence. this field allows for the detection of lost or mis-inserted pm cells containing forward-monitoring information. bip16 the bip-16 error detection code generated over the payloads of the user information cells in the pm block. bcnt block count. this field contains the calculated number of cells in the current pm block. trcc0 total received cell count with clp = 0. trcc0+1 total received cell count. 7.0 oam functions cn8236 7.5 oam control and status structures atm servicesar plus with xbr traffic management 7-18 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? 8-1 8 8.0 dma coprocessor 8.1 overview the dma coprocessor performs high-speed sustained data transfers to and from the host memory space. it is controlled by the segmentation and reassembly coprocessors. the major functions of the dma coprocessor are to transfer data from the host memory (through the pci bus) to the segmentation coprocessor, and to transfer data from the reassembly coprocessor to the host memory space (through the pci bus). in all modes of operation, the dma coprocessor maintains a high level of performance. it uses burst transfers when possible to maximize utilization of the host bus bandwidth, performs byte switching to accommodate misaligned transfers, and carries out concurrent input and output transfers (alternating burst reads and burst writes) to support simultaneous input and output data streams. 8.2 dma read for outgoing messages, dma read cycles move data from host memory to the segmentation coprocessor using a gather dma method. the maximum burst size is thirteen 32-bit words, which correspond to one cell. the burst size can be reduced by setting the max_burst_len field in the pci configuration register at a value less than 13 words. 8.3 dma write for incoming messages, dma write cycles move data from the reassembly coprocessor to host memory using a scatter dma method. the maximum burst size is fourteen 32-bit words, which correspond to one atm cell and a status word appended to pm cells. the burst size can be reduced by setting the max_burst_len field in the pci configuration register at a value less than 13 words. 8.0 dma coprocessor cn8236 8.4 misaligned transfers atm servicesar plus with xbr traffic management 8-2 mindspeed technologies ? 28236-DSH-001-B 8.4 misaligned transfers the reassembly and segmentation coprocessors handle data internally on word addresses. the dma coprocessor must be capable of handling transfers from the pci bus without the same constraint, that is, with data that is not aligned on word boundaries. in addition, the length of the transfer is specified in bytes, not 32-bit words, even though the data bus widths are all 32 bits. to facilitate this, byte-switching logic is used within the cn8236. when the cn8236 specifies a host address with the least significant bits (lsbs) = 00, it is implied that the data is byte aligned. figure 8-1 illustrates how a byte-aligned address would map into the pci host address space for a little endian system. selecting between big and little endian systems is done using the endian [bit 12] in configuration register 0 [config0;0x14]. figure 8-1. little endian aligned transfer atm cell 0 0 1 1 2 2 3 3 4567 4 5 6 7 8 8 9 9 host address = 00 from rsm block 0x00 0x04 0x08 address 10 10 11 11 length(# of 32 bit words) = 3 bytes pci host address space 8236_055 cn8236 8.0 dma coprocessor atm servicesar plus with xbr traffic management 8.4 misaligned transfers 28236-DSH-001-B mindspeed technologies ? 8-3 when the cn8236 specifies a host address with the lsbs not equal to 00, it is implied that the data is misaligned. figure 8-2 illustrates how a misaligned address would map into the pci host address space for a little endian system. figure 8-3 illustrates how a byte-aligned address would map into the pci host address space for a big endian system. figure 8-2. little endian misaligned transfer atm cell 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 host address = 11 0x00 0x04 0x08 0x0c address host address = 10 0x00 0x04 0x08 0x0c 0x0c address host address = 01 0x00 0x04 0x08 address 10 10 10 10 11 11 11 11 length (# of 32 bit words) = 3 pci host address space bytes bytes bytes from rsm block from rsm block from rsm block 8236_056 figure 8-3. big endian aligned transfer 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 0x00 0x04 0x08 address 10 10 11 11 bytes atm cell pci host address space length (# of 32 bit words) = 3 host address = 00 from rsm block 8236_057 8.0 dma coprocessor cn8236 8.5 control word transfers atm servicesar plus with xbr traffic management 8-4 mindspeed technologies ? 28236-DSH-001-B when the cn8236 specifies a host address with the lsbs not equal to 00, it is implied that the data is not aligned. figure 8-4 illustrates how an unaligned address would map into the pci host address space for a big endian system. 8.5 control word transfers if a host system sends control words to the sar in little endian format, the reassembly and segmentation blocks must have the capability of byte swapping to format these control words to or from big endian. control word byte swapping is controlled by bits 30 (master control byte swap, mstr_ctrl_swap) and 29 (slave control byte swap, slave_swap), located in the special status register of the pci configuration space (address 0x40). when slave_swap is a logic high, the slave interface swaps the bytes of a slave write or read access. when mstr_ctrl_swap is a logic high, the control structures that the sar writes are written with bytes swapped. an active hrst* causes these bits to be a logic low. figure 8-4. big endian misaligned transfer atm cell 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 host address = 11 0x00 0x04 0x08 0x0c address host address = 10 0x00 0x04 0x08 0x0c 0x0c address host address = 01 0x00 0x04 0x08 address 10 10 10 10 11 11 11 11 length (# of 32 bit words) = 3 pci host address space bytes bytes bytes from rsm block from rsm block from rsm block 8236_058 28236-DSH-001-B mindspeed technologies ? 9-1 9 9.0 local memory interface 9.1 overview to simplify system implementations, the cn8236 integrates a complete memory controller, designed for direct interface to common srams. the control and status registers and the physical interface devices in the standalone mode of operation are mapped into the bottom of the memory map. consequently, accesses to these resources are also controlled by the memory controller. up to 8 mb of external memory using sram devices can be accessed by the cn8236. the amount of memory required is heavily dependent on the number of vccs implemented and the number of vccs that are currently active. 9.0 local memory interface cn8236 9.1 overview atm servicesar plus with xbr traffic management 9-2 mindspeed technologies ? 28236-DSH-001-B figure 9-1 provides the cn8236 address map. figure 9-1. cn8236 memory map mcs[3]* mcs[2]* mcs[1]* mcs[0]* phycs2* phycs1* (cn8250) (1) (1) cn8236 internal registers (0x7fffffh >> (5-banksize)) (0x600000h >> (5-banksize)) (0x5fffffh >> (5-banksize)) (0x400000h >> (5-banksize)) (0x3fffff >> (5-banksize)) (0x200000h >> (5-banksize)) (0x1fffffh >> (5-banksize)) 0x001800h 0x000800h ? 0x000fffh 0x000200h ? 0x0007ffh 0x000000h ? 0x0001ffh 0x001000h-0x0017ffh internal sram 8236_059 note(s): all addresses in this illustration are byte addresses. (1) these device selects are available in stand-alone mode only; otherwise, this memory is mapped to msc[0]*. cn8236 9.0 local memory interface atm servicesar plus with xbr traffic management 9.2 memory bank characteristics 28236-DSH-001-B mindspeed technologies ? 9-3 9.2 memory bank characteristics the external memory is organized in one to four banks of up to 2 mb each. the system can use any number of banks to fulfill the memory requirements; the only stipulation is that the banks must be of the same size and organization. the local processor and host processor select between the banks using the pbsel[1:0] inputs. pbsel[1:0] is sourced by local processor host processor sources pci address bits. banksize[2:0] (bits 23 ? 21) in the config0 register denote the size of the memory banks and allow the cn8236 to incorporate the various bank sizes into contiguous memory. table 9-1 gives the coding of the banksize[2:0] control bits. the memory controller is designed to work with standard by_8 devices, by_4 sram devices, and by_16 devices. grounding the rammode input selects the by_4 or by_8 mode of operation, while pulling rammode to a logic 1 selects by_16 operation. when by_16 operation is selected, the mwe[3:0]* outputs become byte enables for both reads and writes. when reading local memory, entire 32-bit words are always read, regardless of memory type. figure 9-2 shows a typical 500-kb bank implementation using by_8 sram devices. figure 9-3 shows a typical bank using by_16 ram. to connect different sized ram banks, simply use more or less address bits; all other control remains the same. note: the number and type of sram chips used affect the address and data bus capacitance and, therefore, the ac timing specifications and the required sram speed. the use of by_4 devices causes more address bus loading than the use of by_8 or by_16 devices. see chapter 16.0 , for detailed timing information. table 9-1. memory bank size banksize bank memory organization total bank size (bytes) pbsel[1:0] or pci address bits typical implementation 111 2 m 32 8 m ? future expansion 110 1 m 32 4 m ? two 1 m 16, one 1 m 32 101 512 k 32 2 m a[22:21] four 512 k 8 100 256 k 32 1 m a[21:20] two 256 k 16, eight 256 k 4 011 128 k 32 512 k a[20:19] four 128 k 8 010 64 k 32 256 k a[19:18] two 64 k 16, eight 64 k 4 001 32 k 32 128 k a[18:17] four 32 k 8 000 16 k 32 64 k a[17:16] two 16 k 16, eight 16 k 4 9.0 local memory interface cn8236 9.2 memory bank characteristics atm servicesar plus with xbr traffic management 9-4 mindspeed technologies ? 28236-DSH-001-B figure 9-2. 0.5 mb sram bank utilizing by_8 devices laddr[16:0] ldata[31:0] mcsx* moe* mwe[3]* mwe[2]* mwe[1]* mwe[0]* mwr* a[16:0] d[31:24] d[23:16] d[15:8] d[7:0] /cs /oe /we d[7:0] a[16:0] /cs /oe /we d[7:0] a[16:0] /cs /oe /we d[7:0] a[16:0] /cs /oe /we d[7:0] cn8236 sram sram sram sram rammode gnd 128 k x 8 128 k x 8 128 k x 8 128 k x 8 8236_060 figure 9-3. 1 mb sram bank utilizing by_16 devices laddr[17:0] ldata[31:0] mcsx* moe* mwe[3]* mwe[2]* mwe[1]* mwe[0]* mwr* a[17:0] d[31:16] d[15:0] /cs /oe /we d[15:0] a[17:0] /cs /oe /we d[15:0] cn8236 sram sram /beh /bel /beh /bel rammode pullup 256 k x 16 256 k x 16 8236_061 cn8236 9.0 local memory interface atm servicesar plus with xbr traffic management 9.2 memory bank characteristics 28236-DSH-001-B mindspeed technologies ? 9-5 the memory map contains space allocated to the rs825x (physical layer device), and to a future second mindspeed phy device. this mapping is only valid when the procmode input pin is pulled high, indicating standalone operation with no local processor present. section 10.6 details standalone operation. when procmode is logic low and the local processor is present, addresses 0x1ffh through 0xfffh are available for general use and are mapped to mcs[0] * . the memctrl bit in the config0 register selects the number of wait states that the memory controller uses to access the sram. a logic 0 indicates 0 wait state or single-cycle memory, while a logic 1 indicates one wait state or two-cycle memory. the power-on default is memctrl = 1, selecting one wait state or two-cycle memory accesses. accesses made to the control registers and internal sram by the local processor follow the convention for sram accesses; that is, either 0 or 1 wait state, depending on memctrl programming. subsequently, the local processor sees no functional timing differences between accesses to registers or sram. the internal register accesses from the pci slave interface are always 0 wait state. when the cn8236 decodes a pci slave read to its address space, the cn8236 performs a prefetch of four subsequent (contiguous) word locations. sram access time requirements are directly proportional to the system clock speed and the amount and organization of the memory. the required system clock speed for a given application is dependent on the physical line rate, number of vccs, and the percentage of idle cells versus assigned cells. memory access times and other requirements are specified at three typical implementations of one, two, and four banks of by_8 sram. in terms of address bus loading, one bank of by_8 sram equals one-half bank of by_16 or two banks of by_4. in this way, the system designer can choose the appropriate sram characteristics to suit the amount of memory and organization required for the application. (see chapter 16.0 for timing information.) 9.0 local memory interface cn8236 9.3 memory size analysis atm servicesar plus with xbr traffic management 9-6 mindspeed technologies ? 28236-DSH-001-B 9.3 memory size analysis table 9-2 lists the memory size requirements for 1,024 configured vccs under the following assumptions: segmentation 1. the schedule table is 2,112 schedule slots and each slot is a double word. this allows cbr and three-priority vbr schedule in 64 kbps increments for an oc-3 connection. 2. eight abr templates. 3. 32 oam pm channels active. 4. transmit queues configured for 256 entries. 5. no status queues in sar local memory. 6. each active channel has an average of one active segmentation buffer. 7. rs_queue size is 1,024 entries. reassembly 1. eight vpis per 1,024 channels. 2. 1,024 entries preallocation on vpi = 0 only. 3. uni vpi space. 4. 32 oam pm channels active. 5. free buffer queues configured for 256 entries. 6. no status queues in sar local memory. 7. fbq pools 0-15 have 4-word entries, and pools 16-31 have 2-word entries. table 9-2. memory size in bytes data structure one peer 16 peers 32 peers seg schedule table 16896 16896 16896 seg seg_pm 1024 1024 1024 rs queue 8192 8192 8192 seg transmit queues 1024 16384 32768 seg er tables 67200 67200 67200 rsm free buffer queues 4096 65536 98304 rsm pm-oam 512 512 512 rsm vpi index table 1024 1024 1024 total fixed 99200 176000 225152 seg vcc table 40960 40960 40960 seg buffer descriptors 20480 20480 20480 rsm vcc table 49152 49152 49152 rsm vci index table 92 92 92 total incremental 110684 110684 110684 grand total 209884 286684 335836 28236-DSH-001-B mindspeed technologies ? 10-1 10 10.0 local processor interface 10.1 overview the cn8236 integrated circuit can be used in conjunction with an external processor that performs initialization, link management, monitoring, and control functions. the local processor interface consists of a loosely coupled architecture that interfaces to the cn8236 through bidirectional transceivers and buffers controlled by the local processor and the cn8236, as shown in figure 10-1 . this architecture allows the processor access to all of the cn8236 sar-shared memory and control registers, while insulating the cn8236 from processor instruction and data cache fills. this also allows the local processor the option to control multiple cn8236 and/or physical interface devices. figure 10-1. cn8236 ? local processor interface dir data data data enable dir /oe x32 xcvr /oe address address x17 buff local processor cn8236 high address decode chip select control status control status optional clock clock logic (1) (2) 8236_111 note(s): (1) required to address full 8-mb range. typically, fewer address lines are used. (2) required for non-i960 processors. 10.0 local processor interface cn8236 10.1 overview atm servicesar plus with xbr traffic management 10-2 mindspeed technologies ? 28236-DSH-001-B the processor interface is a generic synchronous interface based on the intel i960ca 32-bit architecture and is completely compatible with the i960ca/cf and the new i960jx processors. other synchronous and asynchronous processors (for example, from motorola, amd, idt) can be interfaced using external circuitry. the only requirement is that the processor have a 32-bit bus and that the control signals be synchronized to sysclk. to access the cn8236 sar-shared memory or control registers, the processor must arbitrate with the cn8236 for access to the memory controller. due to the requirements of reassembly and segmentation access to sram and the implications of pci bus utilization, the local processor has the lowest priority in the memory arbitration scheme. since the local processor is typically used for low bandwidth supervision and maintenance functions, this should be acceptable. when the local processor accesses the cn8236 ? s control registers, internal sram, or sar-shared memory, a local processor memory request is generated internal to the cn8236. the memory arbiter then coordinates this request with requests from other memory consumers and grants the memory bus to the local processor at the appropriate time. the local processor is held off during this process by the insertion of a variable number of wait states, accomplished by the i960 withholding ready* or rdyrcv*. once the local processor is granted the memory system, the transceivers are enabled to allow the local processor ? s address and data to access the sram or control registers. the conclusion of the data transaction is signaled by the assertion of prdy*. wait states can inserted by the processor at any time by asserting pwait * . the last data cycle in a burst is indicated by the pblast* signal. in this manner, non-i960 processor half-speed buses or slow transceivers can be accounted for. the lp_bwait bit in the config0 register automatically adds a single wait state between the first access in a burst and subsequent accesses. this can be used to simplify the design of memory controllers for processors that do not produce a wait output and which require more time between data cycles in a burst. cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.2 interface pin descriptions 28236-DSH-001-B mindspeed technologies ? 10-3 10.2 interface pin descriptions the local processor bus interface consists of the control, address, and status signals described in table 10-1 . refer to table 2-1 and figure 10-7 for further information on these interface pins. table 10-1. processor interface pins (1 of 2) signal dir (1) description procmode i processor interface mode select input ? a logic low on this input enables the local processor mode of operation. pcs* i processor interface chip select ? a logic low on this signal in conjunction with a logic low on pas* at the rising edge of sysclk initiates a memory request to the memory controller. pas* i processor address strobe ? a logic low on this signal in conjunction with a logic low on pcs* latches the value of pwnr, pbsel[1:0], paddr[1:0], and pbe[3:0]* at the rising edge of sysclk. pwnr i processor write/read select ? a logic 1 on this input indicates a write cycle; a logic 0 indicates a read cycle. latched at rising edge of sysclk when pas* and pcs* are active. paddr[1:0] i word select address inputs ? indicates the word address for a single cycle access, or the first word for a multi-cycle burst access. latched at rising edge of sysclk when pas* and pcs* are active. pbsel[1:0] i bank select inputs ? decode to select mcs[3:0]*. latched at rising edge of sysclk when pas* and pcs* are active. 10.0 local processor interface cn8236 10.2 interface pin descriptions atm servicesar plus with xbr traffic management 10-4 mindspeed technologies ? 28236-DSH-001-B pbe[3:0]* i byte select inputs ? active low. allows individual bytes of selected word to be written. not active on reads. latched at rising edge of sysclk when pas* and pcs* active. pbe[3]* controls writes to ldata[31:24]; pbe[2]* controls ldata[23:16]; etc. pwait* i processor wait input ? allows the processor to insert a variable number of wait states to extend memory transaction. must be active on rising edge of sysclk with prdy* active to insert wait cycle. can be used to interface to half speed or slow processor bus or to allow the use of slow transceivers. if insertion of wait states is not required, set this input to a logic high. this signal can only be active, logic low, when pblast* is a logic high. pblast* i processor burst last input ? indicates the last word of a cycle. must be active on rising edge of sysclk with prdy* active to indicate last cycle. if burst accesses and wait cycles generated by pwait* are not required, this signal should be set to a logic low. prdy* o processor interface ready signal ? a logic low on this signal at rising edge of sysclk indicates that the present cycle has been completed. if a read cycle, the data is valid to latch by the processor; if a write cycle, the data has been written and can be removed from the bus. when prdy* is active, wait states can be inserted with pwait*, or a single or burst cycle can be terminated by pblast* (2) . pfail* i the local processor can indicate a failure of its internal self-test or initialization processes by asserting the pfail* input to the cn8236. note(s): (1) direction given with respect to the cn8236. (2) this output corresponds to the ready* or rdyrcv* input in the i960 architecture. 3. the processor system is responsible for controlling the direction of the bidirectional data bus transceiver. in the i960 architecture, this can be controlled by the dt/r* signal. table 10-1. processor interface pins (2 of 2) signal dir (1) description cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.3 bus cycle descriptions 28236-DSH-001-B mindspeed technologies ? 10-5 10.3 bus cycle descriptions throughout the bus cycle descriptions, cycle refers to a single sysclk cycle ending with a rising edge. an arbitration cycle is one in which the memory requests from the local processor and internal memory consumers are compared, and the one with the highest priority is granted the memory access on the next cycle. a memory access that was previously arbitrated might occur on an arbitration cycle. once the local processor has successfully acquired the memory controller, it holds the bus until it is relinquished by the assertion of pblast* on the last data cycle. therefore, local processor burst transfers are always completed, and can theoretically be of arbitrary length. however, in practice, burst transfers should be limited to four or less. the maximum arbitration delay for a local processor access is on the order of 20 cycles; however, it is typically from one to four cycles. this parameter is heavily influenced by the sysclk frequency, line rate, number of vccs, idle cell ratio, and sram access speed. therefore, a system design in which local processor accesses must occur within a fixed time period is not recommended. 10.3.1 single read cycle, zero wait state example figure 10-2 illustrates a single read cycle with 0 wait states. during the address cycle (cycle 1) at the rising edge of sysclk with pcs* and pas* active, a memory request is generated by the processor interface circuitry. also at this time, the read/write select, bank select, and word select inputs (pwnr, pbsel[1:0], and paddr[1:0]) are internally latched. the byte enables (pbe[3:0]*) are don ? t-cares during reads. during cycle 2, this local processor memory request is processed by the memory arbitration circuitry. if no other memory consumers request an access on the same cycle, the local processor is granted access on cycle 3. however, to take into account bus transceiver turnaround, cycle 3 is always a wait or bus recovery state, which gives sufficient time for the address from the processor to access the sram. for 0 wait state sram, unless a wait state is inserted by the processor, the data is available to be latched into the processor on cycle 4, which is indicated by the assertion of prdy*. cycle 5 is an arbitration cycle for the internal memory consumers, which might have requested access during the processor access. it also serves as a bus recovery cycle for the processor. once the pcs*, pas*, pwnr, pbsel[1:0], and paddr[1:0] are sampled at cycle 1, they are don ? t-cares for the remainder of the access. dt/r* is an output supplied by the local processor to indicate the direction of the data transceivers. the cn8236 pdaen* signal is active to enable data and address. 10.0 local processor interface cn8236 10.3 bus cycle descriptions atm servicesar plus with xbr traffic management 10-6 mindspeed technologies ? 28236-DSH-001-B figure 10-2. local processor single read cycle ta tarb tbr td tbr/tabr sysclk pcs* pas* pwnr pbsel[1:0] paddr[1:0] pbe[3:0] dt/r* pwait* pblast* prdy* d[31:0] a[20:4] laddr[18:2] laddr[1:0] ldata[31:0] pdaen* mcs*[3:0] moe* mwe*[3:0] 0111 d0 10 a0 a0 d0 11 10 address cycle 1. arbitration cycle 2. bus recovery cycle 3. 4. data cycle 5. bus recovery next arbitration cycle 8236_062 cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.3 bus cycle descriptions 28236-DSH-001-B mindspeed technologies ? 10-7 10.3.2 single read cycle, wait states inserted by memory arbitration figure 10-3 illustrates a local processor single read cycle with arbitration wait states. this example is similar to the preceding one, except that here the local processor is not able to access the ram immediately because of higher priority memory requests on cycles 2 and 3. on cycle 4, the memory controller allows the local processor access to the address and data bus, and the transaction takes place at the end of cycle 6. figure 10-3. local processor single read cycle with arbitration wait states 123 4567 sysclk pcs* pas* pwnr pbsel[1:0] paddr[1:0] pbe[3:0] dt/r* pwait* pblast* prdy* d[31:0] a[20:4] laddr[18:2] laddr[1:0] ldata[31:0] pdaen* mcs*[3:0] moe* mwe*[3:0] ta tarb tbr td tarb tarb tarb 11 10 a0 d0 a0 10 d0 0111 address cycle 1. arbitration cycle 2. arbitration cycle 3. arbitration cycle 7. arbitration cycle 4. bus recovery cycle 5. 6. data cycle 8236_063 10.0 local processor interface cn8236 10.3 bus cycle descriptions atm servicesar plus with xbr traffic management 10-8 mindspeed technologies ? 28236-DSH-001-B 10.3.3 double read burst with processor wait states in figure 10-4 , the processor inserts wait states on cycle 4 and cycle 6 to allow additional time for the reads to occur. at the rising edge of sysclk on cycle 4 and cycle 6, the combination of pwait* low and prdy* low extends the read by one more cycle. the local processor word select inputs (paddr[1:0]) are latched at cycle 1. the cn8236 word select address lines, laddr[1:0], are incremented automatically at the beginning of cycle 6. figure 10-4. local processor double read with wait states inserted sysclk pcs* pas* pwnr pbsel[1:0] paddr[1:0] pbe[3:0] dt/r* pwait* pblast* prdy* d[31:0] a[20:4] laddr[18:2] laddr[1:0] ldata[31:0] pdaen* mcs*[3:0] moe* mwe*[3:0] ta tarb tbr tw td td tw d0 d1 1101 10 00 a0 a0 00 d0 01 d1 address cycle 1. arbitration cycle 2. bus recovery cycle 3. data cycle 7. wait cycle 4. data cycle 5. 6. wait cycle 234567 1 8236_064 cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.3 bus cycle descriptions 28236-DSH-001-B mindspeed technologies ? 10-9 10.3.4 single write with one-wait-state memory in figure 10-5 , the local processor performs a single write into one-wait-state memory. there is no arbitration delay. rammode is a logic high, indicating that by_16 ram is used. here the pbe[3:0]* inputs are latched at cycle 1, and are used to select the byte enables that are active during the cycle when mwr* is active. in this case, the two most significant bits are active, indicating a 16-bit write to the two most significant bytes. figure 10-5. local processor single write with one wait state by_16 sram 1 2 34 5 sysclk pcs* pas* pwnr pbsel[1:0] paddr[1:0] pbe*[3:0] dt/r* pwait* pblast* prdy* d[31:0] a[20:4] laddr[18:2] laddr[1:0] ldata[31:0] pdaen* mcs*[3:0] moe* rammode mwe*[3:0] mwr* ta tarb tbr tw td d0 1110 0011 d0 a0 a0 01 00 01 0011 address cycle 1. arbitration cycle 2. bus recovery cycle 3. wait cycle 4. data cycle 5. 8236_065 10.0 local processor interface cn8236 10.3 bus cycle descriptions atm servicesar plus with xbr traffic management 10-10 mindspeed technologies ? 28236-DSH-001-B 10.3.5 quad write burst, no wait states in figure 10-6 , a quad burst write access to 0-wait-state memory is illustrated. rammode is logic low, selecting by_8 or by_4 ram mode. here pbe[3:0]* is latched on cycle 1, indicating that the write is active on all bytes, and the mwe*[3:0] outputs are active as write strobes while mwr* is not used. the sar-shared memory word select addresses, laddr[1:0], are incremented automatically by the cn8236 on each successive write cycle. although the i960 architecture has the limitation that a quad word transfer must start on a quad word boundary, the cn8236 does not have that limitation. thus, the paddr[1:0] bits can be any value and are incremented as long as the burst transfer proceeds. figure 10-6. local processor quad write, no wait states 1234567 sysclk pcs* pas* pwnr pbsel[1:0] paddr[1:0] pbe[3:0] dt/r* pwait* pblast* prdy* d[31:0] a[20:4] laddr[18:2] laddr[1:0] ldata[31:0] pdaen* mcs*[3:0] moe* rammode mwe*[3:0] ta tarb tbr td td td td d0 d1 d2 d3 address address 00 01 10 11 d0 d1 d2 d3 1011 f 0 f 0 f 0 f 0 f 01 00 0000 address cycle 1. arbitration cycle 2. bus recovery cycle 3. data3 cycle 7. data cycle 4. data1 cycle 5. 6. data2 cycle 8236_066 cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.4 processor interface signals 28236-DSH-001-B mindspeed technologies ? 10-11 10.4 processor interface signals figure 10-7 illustrates the signal interface between the cn8236 device and the i960ca/cf processor. the memory region decoded for pcs* should be set for n rad and n wa d = 2, n rdd and n wdd = 0 or 1 (depending on the use of 0 or 1 wait state sram), and n xda = 1. in addition, external ready control must be enabled, and burst can be enabled or disabled at the system designer ? s option. pulling up the i960 clkmode input to a logic 1 selects the divide-by-one clock mode, making i960 pclk synchronous to sysclk. 10.0 local processor interface cn8236 10.4 processor interface signals atm servicesar plus with xbr traffic management 10-12 mindspeed technologies ? 28236-DSH-001-B figure 10-7. i960ca/cf to the cn8236 interface i960ca/cf a[2] a[3] sram a[20:4] a[1] a[0] a[18:2] paddr[0] paddr[1] laddr[18:2] laddr[1] laddr[0] d[31:0] ldata[31:0] d[31:0] a[22:21] pbsel[1:0] ready* be[3:0]* blast* prdy* pbe[3:0]* pblast* wait* pwait* w/r* pwnr reset* xint0 fail* as* clkin prst* pint* pfail* pas* sysclk we[3:0] mwe[3:0]* moe* oe sramcs* sramcs* sramcs* sramcs* mcs[3]* mcs[2]* mcs[1]* mcs[0]* dt/r* pcs* decode x32 xcvr x17 buff (1) pdaen* mwr* for by_16 sram a[31:28] clkmode pullup procmode gnd rammode gnd for by_8 or by_4, vcc for by_16 pclk nc cn8236 8236_112 note(s): (1) required for full 8 mb address range. cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.5 local processor operating mode 28236-DSH-001-B mindspeed technologies ? 10-13 this configuration is for addressing the entire 8 mb of sram. in the majority of systems, the sram requirements is considerably less. the implications of this are that the pbsel[1:0] inputs can be driven by lower order address lines, and there are less than 17 address lines to buffer. therefore, in most applications, the data transceivers can utilize two x_16 parts, such as a 74abt16245, and the address buffer can utilize a single x_16 74abt16244. note: the i960ca/cf signals a failure of its internal self-test upon reset or power-up, by asserting its fail* output. this line is connected to the pfail* pin of the cn8236, and the status of this pin is reflected in the host interrupt status register [host_istat0; 0xc0]. 10.5 local processor operating mode the major difference between the i80960jx processor and the i80960ca is that the i80960jx utilizes a multiplexed address/data bus structure, while the i80960ca/cf is non-multiplexed. however, in the cn8236 system, the de-multiplexing of address/data takes place on the processor side of the address buffers and, therefore, does not affect the cn8236. otherwise, the i80960jx has the same bus control signals as the i80960ca/cf with the exception of the wait* signal, which the i80960jx does not possess. the insertion of wait states, if required, must be accomplished by an external memory controller, which in any case, is required for a i80960jx implementation. 10.0 local processor interface cn8236 10.6 standalone operation atm servicesar plus with xbr traffic management 10-14 mindspeed technologies ? 28236-DSH-001-B 10.6 standalone operation standalone interface pins and descriptions are given in table 10-2 . figure 10-8 shows the signal interface between the cn8236 and the rs825x atm receiver/transmitter device with no local processor. the pcs*, pas*, and pwnr pins are now outputs providing chip select, address strobe, and write/read control to the rs825x. pdaen* is now an input connected to the interrupt sources of the rs825x. pblast* is a second chip select, which can be used to connect a future second mindspeed phy device. the prdy* output is active and indicates the cycles in which the data transaction occurs. the pwait* input is active and can be used to prolong the cycle (as shown in figure 10-9 ). physical interface devices other than the rs825x can be connected by using pwait* to extend the read or write cycle, and by using external logic to translate the cn8236 control signals. table 10-2. standalone interface pins signal dir (1 ) description procmode i processor interface mode select input. a logic 1 enables standalone operation without a local processor. pcs* o chip select output for phy device number 1. synchronous to sysclk. pblast* o chip select output for phy device number two. synchronous to sysclk. pas* o phy address strobe. synchronous to sysclk. pwnr o phy write/read select. a logic 1 on this output indicates a write cycle, a logic 0 indicates a read cycle. synchronous to sysclk. prdy* o phy interface ready signal. a logic low on this signal at rising edge of sysclk indicates that the data cycle has been completed. pwait* i phy wait input. allows external logic to insert wait states to extend data cycles. only active when prdy* is active. pdaen* i phy interrupt input, active low, level sensitive (2) . paddr[1:0] i not used, pull to logic 0. pbsel[1:0] i not used, pull to logic 0. pbe[3:0]* i not used, pull to logic 0. pfail* i not used, pull to logic 1. note(s): (1) direction given with respect to the cn8236. (2) see the host_istat0 register for details. cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.6 standalone operation 28236-DSH-001-B mindspeed technologies ? 10-15 figure 10-8. cn825x and sar (cn8236) interface (standalone operation) cn825x cn8236 sar sram paddr[0] paddr[1] data[7:0] ldata[31:0] pbsel[1:0] cs* w/r*, rd* as*, wr* prdy* pbe[3:0]* pblast* mclk, clksel pwait* pwnr prst* pdaen* pfail* pas* sysclk a[18:0] d[31:0] laddr[18:0] addr[6:0] sramcs* sramcs* sramcs* int* we[3:0]* mwr[3:0]* oe* moe* sramcs* mcs[3]* mcs[2]* mcs[1]* mcs[0]* reset* pcs* pullup n/c (2) gnd gnd gnd gnd open pullup procmode mwr* for x16 sram rammode gnd for x_8 or x_4 pullup for x_16 pullup pullup (1) syncmode fiber pmd or cat 5 pci bus device txdata[7:0] txdata[15:8] txclav txenb* txsoc txprty txaddr[4:0] utoptxclk utoprxclk rxdata[7:0] rxdata[15:8] rxclav rxenb* rxsoc rxprty rxaddr[4:0] txd[7:0] txclav txen txpar clkd3 rxd[7:0] rxclav rxen* rxsoc rxpar gnd gnd open gnd vcc 8236_113 note(s): (1) can be driven by external circuitry to extend cycles. (2) can be used by external circuitry. txsoc 10.0 local processor interface cn8236 10.6 standalone operation atm servicesar plus with xbr traffic management 10-16 mindspeed technologies ? 28236-DSH-001-B figure 10-9. cn8236/phy functional timing with inserted wait states ta tw tw td write address write data 12 345 sysclk pcs* pas* pwnr pwait* prdy* laddr[13:0] ldata[7:0] 8236_067 cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.6 standalone operation 28236-DSH-001-B mindspeed technologies ? 10-17 figure 10-10 shows a read and write rs825x access. at cycle 1 (the rising edge of sysclk) the rs825x samples pcs*, pas*, and pwnr low, indicating a read cycle. by the next rising edge of sysclk at cycle 2, the data is output by the rs825x to be latched by the cn8236. the same procedure occurs for a write except that at cycle 4, pwnr is sampled high. the rs825x then latches the data to the appropriate internal register on the next sysclk rising edge at cycle 5. figure 10-10. cn8236/rs825x read/write functional timing ta td ta td read address write address read data write data 1 2 34 5 6 sysclk pcs* pas* pwnr pwait* prdy* laddr[13:0] ldata[7:0] 1, 2 read cycle 4, 5 write cycle 8236_068 10.0 local processor interface cn8236 10.6 standalone operation atm servicesar plus with xbr traffic management 10-18 mindspeed technologies ? 28236-DSH-001-B 10.6.1 microprocessor interface for multiple physical devices multi-phy or extended addressing for a phy is provided through a phy page mechanism. this allows address bits to be appended to phy control access without increasing the size of the phy memory map as seen by the pci. the phy bank field in the config1 control register provides up to 5 bits of page addressing for a total of 14 bits of phy addressing. the contents of phy bank are placed on laddr[13:9] during phycs1 or phycs2 accesses. figure 10-11 illustrates control connections between the sar and a phy device. figure 10-11. sar/peak 8 control connections pdata[7:0] pcs* pas* cn8228 (peak8) cn8236 (sar) pwnr pint* pwait* pullup pullup prst* pclk (had[10:3])paddr[7:0] data[7:0] cs* as* wnr int* syncmode reset* mclk addr[7:0] paddr[12:8] addr[12:8] (1) 8236_114 note(s): (1) cn8236 (sar) outputs 5 bits, cn8228 (peak8) only uses 4 bits. cn8236 10.0 local processor interface atm servicesar plus with xbr traffic management 10.7 system clocking 28236-DSH-001-B mindspeed technologies ? 10-19 10.7 system clocking the cn8236 derives all of its timing from a 2x clock input, clk2x. this clock is internally divided by two to create the system clock, sysclk. this system clock is used internal to the device, and is output to the system to provide the clock to an external processor or phy device. all processor interface signals are synchronous to sysclk. in addition, clkd3 (clk2x asymmetrically divided by three, an output clock), is provided, and can be used as the clock for the utopia atm physical interface. alternatively, sysclk can be used as the clock source for the utopia atm physical interface. in either case, the clock signal would be looped externally to rxclk and txclk (if mult_clr set low, txclk is not used). for example, if clk2x is 66 mhz, then clkd3 is 22 mhz, and is suitable for the utopia interface. if clk2x is 50 mhz, then sysclk is 25 mhz and is suitable for the utopia interface. the clk2x frequency required for a given application is a function of the physical line rate, number of vccs, active concurrent vccs, and the sram cycle time. 10.8 real-time clock alarm a real-time clock counter and alarm registers are built into the cn8236. this real-time clock consists simply of a 7-bit pre-scaler (configured via the divider field in the config0 register) that accepts the sysclk input and outputs a constant (nominally 1 mhz) pulse train, and a 32-bit read/write counter (the real-time clock register [clock;0x00]), that counts the number of pulses output by the pre-scaler since the system was initialized. when the pre-scaler is set to generate a 1 mhz pulse train, the clock counter counts in 1 s intervals. an interrupt is generated when the clock counter overflows, that is, more than 2 32 pulses have occurred since it was cleared to 0. if this happens, the clock counter simply wraps around to 0 and starts counting over. the control processor or host software is responsible for noting the overflow. one simple real-time alarm is implemented in the cn8236. this is alarm register 1 [alarm1;0x04], which is continuously compared to the clock register. when a match is detected, the corresponding interrupt is generated to the local or host processors. either processor can then respond to this interrupt and reload a new value into the alarm1 register. 10.0 local processor interface cn8236 10.9 cn8236 reset atm servicesar plus with xbr traffic management 10-20 mindspeed technologies ? 28236-DSH-001-B 10.9 cn8236 reset the cn8236 must be reset by the host processor prior to system initialization for proper operation. this can be done in one of two ways: by asserting the external hrst* pin (which is normally connected to the system power-up reset circuitry), or by setting the global_reset bit in the configuration register 0 [config0;0x14]. the hrst* pin must be deasserted and global_reset must be cleared before beginning the cn8236 initialization process. asserting the hrst* input pin automatically causes the local processor reset pin to be driven active. the reset to the local processor stays active until the lp_enable bit in the config0 register is set to a logic high. when using the global_reset bit, the processor must manually set or clear the appropriate bits in the config0 register. 28236-DSH-001-B mindspeed technologies ? 11-1 11 11.0 pci bus interface 11.1 overview the pci bus interface is compliant with pci local bus specification , revision 2.1. with the exception of hrst* and hint*, this interface is completely synchronous to the pci bus clock (hclk). all inputs are sampled at the rising edge of hclk, and all outputs are driven by the cn8236 to be valid before the next rising edge of hclk. the maximum pci bus clock rate supported by the cn8236 is 33 mhz. the pci bus interface logic is clocked directly from the pci bus clock, while the remainder of the cn8236 logic runs off separate clocks. synchronizing registers and fifos are implemented in the pci bus interface in order to transfer data between the pci bus clock (hclk) and the system (sysclk) clock domains. the pci bus drivers are shared between master and slave bus interface functional blocks. the pci bus master logic (within the device) arbitrates via the pci bus arbiter (external to the device) for access to the pci bus; access to the pci bus automatically implies access to the bus drivers, since no other master can be concurrently communicating with the slave logic. the bus master logic contends for the bus on a transaction-by-transaction basis. the pci bus interface responds to read and write requests by the host cpu, allowing access to chip resources by host software. the cn8236 can also act as dma bus master on the pci bus. as a result, the pci bus interface implements the full set of address, data, and control signals required to drive the bus as master, and contains the logic required to support arbitration for the pci bus. the dma coprocessor and the pci bus interface are closely linked and, hence, are shown as one unit. 11.0 pci bus interface cn8236 11.1 overview atm servicesar plus with xbr traffic management 11-2 mindspeed technologies ? 28236-DSH-001-B the pci bus interface functional blocks are as follows: i/o drivers and receivers that drive the pins connected to the pci bus signals. pci bus master logic that allows the bus interface to acquire mastership of the pci bus and act as a transaction initiator. the bus master logic also contains a command decoder that interprets access commands generated by the dma coprocessor, and a burst controller for controlling the duration of each read or write burst. in addition, the bus master logic contains address counters that allow it to restart and retry burst transfers if required by the transaction target. burst fifo buffers that store and transfer bursts of data words between the dma coprocessor and the pci bus master logic. pci bus slave logic that responds to transactions initiated by other masters on the pci bus with the cn8236 as a target. the bus slave logic also synchronizes data passed back and forth across the clock boundary between the pci bus interface and the internal chip logic. configuration registers holding initialization parameters and pci bus status information. logic that allows the host cpu to read/write the internal cn8236 registers via the pci slave port. logic to enable read/write access to the sar-shared memory space from the host cpu, again via the pci slave port. an interface module that allows the pci core to connect to a serial eeprom. cn8236 11.0 pci bus interface atm servicesar plus with xbr traffic management 11.2 unimplemented pci bus interface functions 28236-DSH-001-B mindspeed technologies ? 11-3 11.2 unimplemented pci bus interface functions the pci bus interface on the cn8236 does not implement all transaction types defined by the pci bus specification; only those sections of the protocol that are necessary for slave and dma memory accesses are implemented. in particular, the following transaction types are not implemented: 64-bit transfers, and the dual address cycle command. snooping and cache support. memory read line, memory write, and invalidate commands are internally aliased to the memory read and memory write commands as per the pci specification. locked and exclusive accesses: the pci lock* line is not driven by the cn8236, and the pci slave interface does not handle locked accesses by other bus masters in any special manner. i/o accesses (the i/o read and i/o write commands). interrupt acknowledge cycles, including the interrupt acknowledge command. the special cycle command and special cycle transactions. burst transfers that do not have simple, sequentially incrementing addresses for consecutive data phases. the pci master logic always performs sequentially incrementing burst transfers. the two lsbs of the pci address lines (ad[1,0]) must be 0 during the address phase of any transfer made to the pci slave logic (indicating sequentially incrementing burst addresses). if ad[1,0] is not equal to 0, the slave logic signals a type a or b target disconnect after the first data phase, forcing the external master to perform a single word transfer as per the pci specification. implement sections 3.1.8 and section 7.2 of compact pci hot swap specification . assume that a logic low on the hswitch* input is switch locked and a logic high is switch unlocked. note: the arming/disarming of the ins/ext bits provides a switch debounce function. 11.0 pci bus interface cn8236 11.3 pci configuration space atm servicesar plus with xbr traffic management 11-4 mindspeed technologies ? 28236-DSH-001-B 11.3 pci configuration space in accordance with the pci bus specification , revision 2.1, the cn8236 pci bus interface implements a 128-byte configuration register space. these configuration registers can be used by the host processor to initialize, control, and monitor the sar bus interface logic. the complete definitions of these registers and the relevant fields within them is given in the pci bus specification. (the descriptions and definitions of these register fields as implemented in the cn8236 are provided in chapter 14.0 .) the incoming dma fifo size is programmable and can be set to 2 kb or 8 kb depending on the value of the incfifo_sz bit in the config1 register. 11.4 pci bus master logic the pci bus master logic block is responsible for accepting read and write commands from the dma coprocessor (passed via the burst fifo buffers), and in turn acquiring mastership of the pci bus and generating transactions to perform the actual data transfers. the bus master logic contains the following: a command decoder that interprets commands issued from the dma coprocessor. a burst controller that counts off read and write cycles in each burst on the pci bus (and also latches and drives the address and command during the address phase of each transfer). arbitration logic that acquires control of the pci bus. supported arbitration parking. a bus state machine that sequences and controls transfers. it is possible for the addressed slave to request a disconnect or a retry during a read or a write transfer, using the defined pci protocol sequence. in this case, the bus master logic terminates the current burst, maintain its bus request, and restarts the transfer at the point of termination. disconnects and retries are not regarded as errors. cn8236 11.0 pci bus interface atm servicesar plus with xbr traffic management 11.4 pci bus master logic 28236-DSH-001-B mindspeed technologies ? 11-5 five possible sources of error are present during any pci bus master transaction. if any of the following five errors occur, the bus master logic permanently terminates the transaction, flags an error, and ceases to process any more commands. 1. target abor t ? the pci transaction terminates if the addressed target signals a target abort. in this case, the rta and merror bits in the pci configuration register space are set, and the pci_bus_status[4] bit in the sys_stat register is set. 2. master abort ? if the addressed target does not respond with an hdevsel* assertion, a master abort is flagged. in this case, the rma and merror bits in the pci configuration register space are set, and the pci_bus_status[3] bit in the sys_stat register is set. 3. parity error ? if the data parity checked during read transfers is inconsistent with the state of the hpar signal, then a parity error is signaled. in this case, the dpr and merror bits in the pci configuration register space are set and the pci_bus_status[2] bit in the sys_stat register is set. 4. interface disabled ? if the driver or application software on the pci host cpu has been disabled, the cn8236 pci bus master logic (using the m_en bit in the command field of the pci bus configuration registers), any attempt to perform a dma transaction to the pci bus results in an error. in this case, the merror and intf_dis bits in the pci configuration space are set, and the pci_bus_status[1] bit in the sys_stat register is set. 5. internal failure ? upon a synchronization error between the dma coprocessor and the pci master logic, an internal failure is flagged. in this case, the merror and int_fail bits in the pci configuration space are set, and the pci_bus_status[0] bit in the sys_stat register is set. note: the above errors permanently affect system level operation. because of this, the system should be re-initialized, since full system-level recovery is unlikely. the bus protocol errors can be cleared either by a software reset of the associated status flag or flags (rta, rma, or dpr) or with a reset of the pci bus master logic using the hrst* input pin. for example, a master abort error can be cleared by writing a logic 1 to the rma status bit in the pci configuration register space, causing the status bit to be cleared. internal failures (attempting to initiate a master transaction with the interface disabled, or loss of synchronization with the dma controller) can only be reset by applying the global reset, config0 (global_reset), or by asserting the hrst* signal. next, the merror bit must be cleared. the merror bit in the pci configuration register drives the pci_bus_error interrupt. to clear this interrupt, a logic high must be written to the merror bit location. the merror bit can also be cleared by a logic low on the hrst* input pin. the local processor can clear the error bits by setting config0 (pci_err_reset) to a logic high. after the errors have been cleared, the sar must be re-initialized. 11.0 pci bus interface cn8236 11.5 burst fifo buffers atm servicesar plus with xbr traffic management 11-6 mindspeed technologies ? 28236-DSH-001-B several fields are provided in the pci configuration space to aid in recovering from a pci master error. the pci host software can determine that an error occurred by checking the merror bit. it can also determine if the transaction was a read or write by inspecting the mrd bit, and then retrieve the read or write address at which an error occurred by reading the master_read_addr or master_write_addr fields. the pci read and pci read multiple commands issued by the pci block are under the control of pci_read_multi bit 22 in the config0 register. 11.5 burst fifo buffers two small fifo buffers are implemented to support pci slave burst-mode operation (read = 8 32, write = 64 32), to allow synchronization between the cn8236 internal logic and the pci bus interface, and to carry commands from the dma coprocessor to the pci bus logic. the incoming master fifo is 512 32 or 2 k 32 bits, the outgoing master fifo is 16 36 bits. 11.6 pci bus slave logic the pci slave logic permits the host cpu on the pci bus to access and modify cn8236 resources (the external sar-shared memory, internal memory, and internal registers). because the control processor also has access to these resources, the pci slave logic must arbitrate for access prior to performing any read or write transaction. the slave logic also contains the pci configuration registers. these registers control the pci slave and master interfaces, and can be read or written at any time by the pci host. the slave logic implements the synchronizers required for rate-matching between the pci bus clock and the internal cn8236 system clock. also, small fifos are used to speed up burst reads (8 32) and writes (64 32) performed by the host processor to local resources, by buffering prefetched read data and absorbing latency during consecutive writes. in general, the pci slave interface functions as a normal memory-mapped pci target, responding to memory read, memory write, configuration read, and configuration write commands from any initiator on the pci bus. the slave interface responds only to memory read and memory write commands if the ms_en bit of the command field in the pci configuration register has been set. the pci slave logic does not implement special cycle commands, or respond to special cycles on the pci bus. if a master performs a special cycle on the pci bus, the following occurs: the slave logic never asserts hdevsel*. parity errors during the address phase of the special cycle command are reported to be asserting hserr* in the normal fashion, if se_en and pe_en in the command register are both set. parity errors during the data phase are ignored. cn8236 11.0 pci bus interface atm servicesar plus with xbr traffic management 11.7 byte swapping of control structures 28236-DSH-001-B mindspeed technologies ? 11-7 11.7 byte swapping of control structures two control bits in the pci configuration space are used to configure byte swapping, in order to align with various big and little endian host system requirements. the slave_swap control bit is bit 29 of address offset 0x40 in the pci configuration register. when slave_swap is set to a logic high, the slave interface swaps the bytes of a slave write or read access. the default setting for this bit is logic low. the mstr_ctrl_swap control bit is bit 30 of address offset 0x40 in the pci configuration register. when mstr_ctrl_swap is set to a logic high, the control structures that the sar writes are written with bytes swapped. the default setting for this bit is logic low. the hrst* pin made active causes both of these bits to be logic low. 11.8 power management power management, as a defined class of functions, consists of mechanisms in software and hardware to minimize system power consumption, manage system thermal limits, and maximize system battery life. the cn8236 supports power management on the pci bus according to the pci bus power management interface specification , revision 1.0. power management states are defined as varying, distinct levels of power savings. the cn8236 device supports the two mandatory power states, d0 and d3, of the pci bus power management interface specification. d0 is the maximum powered state (on) and d3 is the minimum powered state (off). when in the d3 state, sysclk is turned off. refer to section 14.7 for the detailed information on the pci configuration space and pci registers concerned with implementing the power management functions. power management is enabled by default. this capability can be disabled via bit 2 of the eeprom (disable capability register), which sets bit 20 of the pci status register to a logic low. see the pci bus power management interface specification , revision 1.0, for specific information on the functions involved in power management. 11.0 pci bus interface cn8236 11.9 interface module to serial eeprom atm servicesar plus with xbr traffic management 11-8 mindspeed technologies ? 28236-DSH-001-B 11.9 interface module to serial eeprom the interface module implements the protocol to allow the pci core to connect to a serial eeprom. a condition can arise where the protocol is violated and unknown operation of the eeprom can occur. if hrst* is applied while the eeprom is being accessed, that is, right after hrst* goes inactive, the access is abnormally terminated with indeterminate effects on the eeprom. in order to reset the eeprom, its power must be cycled. a 12 ma pin, eepwr, is added to supply power to the eeprom if the above condition cannot be guaranteed from happening. whenever hrst* is active, eepwr is a logic low. when hrst* goes to a logic high (inactive), eepwr immediately goes to a logic high. figure 11-1 illustrates a suggested connection of the eeprom. figure 11-1. eeprom connection eepwr sda scl eeprom sar r r v cc 8236_069 cn8236 11.0 pci bus interface atm servicesar plus with xbr traffic management 11.9 interface module to serial eeprom 28236-DSH-001-B mindspeed technologies ? 11-9 11.9.1 eeprom format the first 32 bytes of the 128-byte eeprom are used to store pci configuration information, loaded into the pci configuration space at reset. unless otherwise specified, all unused bytes are reserved and should be programmed to 0x00. bytes above address offset 0x20 can be used by application software or device drivers as needed. the eeprom fields are described in table 11-1 . 11.9.2 loading the eeprom data at reset at reset, the pci configuration block first reads byte 0x00 of the eeprom to determine which fields of the eeprom should be read. it first looks at the field_enables bits. if bit 2 is set, it sets bit 20 in the pci status register to 0, to disable power management capabilities. it then looks at bits 1 and 0 to see if the corresponding svid and/or sid fields are to be loaded into the corresponding pci configuration register fields. if either of these is set to 0, the subsystem_id and/or subsystem_vendor_id fields defaults to all 0s. table 11-1. eeprom fields address offset name description 0x00 field_enables bit 5 ? load memory size mask from eeprom. bit 4 ? load latency timer from eeprom. bit 3 ? load general enables from eeprom. bit 2 ? disable capability registers (for power management). bit 1 ? load subsystem id (sid) from eeprom. bit 0 ? load subsystem vendor id (svid) from eeprom. 0x01 ? 0x03 reserved set to zeros. 0x04 ? 0x05 svid subsystem vendor id. 0x06 ? 0x07 sid subsystem id. 0x08 general enables bit 4 ? special status register bit 29 (slave_swap, slave control byte swap). bit 3 ? special status register bit 30 (mstr_ctrl_swap, master control byte swap). bit 2 ? pci command register bit 6 (pe_en, enable detection of parity errors). bit 1 ? pci command register bit 2 (m_en, master enable). (1) bit 0 ? pci command register bit 1 (ms_en, memory space enable). (1) 0x09 latency timer master latency timer 0x0a memory size mask valid mask values: bit 7 6 5 4 3 2 1 0 = size x 0 0 0 0 0 0 0 = 8 m note(s): (1) system bios is typically responsible for setting these bits after programming the pci base address register. 11.0 pci bus interface cn8236 11.9 interface module to serial eeprom atm servicesar plus with xbr traffic management 11-10 mindspeed technologies ? 28236-DSH-001-B 11.9.3 accessing the eeprom the eeprom is accessed through the pci configuration space at offset 0x4c, the eeprom register. see section 14.7 for a description of the eeprom register ? s contents. see table 14-16 for a description of register 4c. before starting an eeprom operation, the busy bit must be a logic 0 (not busy). when in this state, the eeprom can be either written to or read from. after initiating a read or write operation, the busy bit is a logic 1 (busy) until the transfer completes. during this time, the application software must poll the busy bit to determine when the transfer has completed. once completed, the no_ack bit indicates the status of the operation. a logic 1 (no acknowledge) indicates that no device responded to the request. to initiate a write operation, the application software must write the byte_addr and data fields and set the read_write bit to 0. the module then transfers the data in bits 7:0 (the data field) to the device on the bus at the hardware address at the byte_addr specified. application software then polls the register until the busy bit is read as 0 (not busy), which indicates that the transfer has completed. software must then check the no_ack bit to ensure that the transaction completed normally. if not, the software should retry the transaction or signal the error to the user. since the eeprom might not respond until after a few milliseconds after a write transaction, it is recommended that all operations resulting in no_ack = 1 be retried several times before issuing the failure. for read operations the application software must also write to the eeprom register, specifying the byte_addr to be read and setting the read_write bit to 1. the software must then poll the busy bit until the operation completes. at this point, the data is returned in the data field of the eeprom register. the software should check the no_ack bit to ensure proper completion of the transfer with no error. explanation of series eeprom clock: 11.9.4 using the subsystem id without an eeprom for applications that can utilize bios or boot code to initialize devices before loading high-level operating system software, the cn8236 allows for the programming of the pci configuration space fields, subsystem_id and subsystem_vendor_id. this feature allows a user to employ the cn8236 without an eeprom, but still allows for unique subsystem ids. to program the subsystem_id and subsystem_vendor_id fields, bios must first write a logic 1 to bit 31 of the pci special status register. this enables the writing to these two fields in the pci configuration space. bios can then update the ids by writing the desired values to the pci configuration space at offset 0x2c. once the values are written, bios should then disable the writing to these fields by setting bit 31 of the pci special status register to logic 0. when bit 31 is set to 0, writes to these two fields are ignored. scl pci 84 ? () 4 ? 98.2 khz @pci 33mhz = () == cn8236 11.0 pci bus interface atm servicesar plus with xbr traffic management 11.10 pci host address map 28236-DSH-001-B mindspeed technologies ? 11-11 11.10 pci host address map the address map of the cn8236 resources seen by the pci bus is the same as that seen by the host processor. the base address of the cn8236 resource mapping is defined in the base_address_register_0 field, located in the pci configuration space. burst reads of the control and status registers only return valid data for the first address. subsequent data words read during a burst read are indeterminate. 11.0 pci bus interface cn8236 11.10 pci host address map atm servicesar plus with xbr traffic management 11-12 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? 12-1 12 12.0 atm utopia interface 12.1 overview of atm utopia interface the atm utopia interface contains receive and transmit interface logic and receive error detection logic. the atm utopia interface block also interfaces with the segmentation and reassembly coprocessors. the atm utopia interface for the cn8236 accepts 52 octet cells from the segmentation coprocessor and transmits them to the phy device while inserting a dummy hec. the interface also receives 53 octet cells from the phy device, removes the hec, and saves them in a fifo buffer to be used by the reassembly coprocessor. the atm utopia interface is responsible for communicating with and controlling the atm link interface device, which carries out all the transmission convergence and physical media-dependent functions defined by the atm protocol. the block performs the following functions: receives and transmits atm utopia interface logic. the atm utopia interface accommodates mindspeed rs825x, rs8228, or bt8223 physical layer devices, a utopia-compatible framer or a mindspeed-conceived slave utopia interface, and is responsible for converting between these devices and the internal data interfaces. the slave utopia interface connects the cn8236 to a cell-switched backplane. receives cell synchronization logic, which validates cell boundaries in the incoming byte stream, strips off the hec byte from the atm header, and formats the remaining 52 bytes into thirteen 32-bit words before passing them to the incoming cell fifo buffer. the receive cell synchronization logic ensures that only complete cells are passed down to the remainder of the reassembly controller. transmits cell synchronization logic, which converts the 32-bit data read from the transmit cell fifo buffer into 8- or 16-bit (plus parity) streams, generates appropriate cell delineation pulses for use by the transmit atm utopia interface, and inserts the blank hec byte into the atm header of each cell prior to transferring it to the utopia interface. generates and checks odd parity on the octet transmit and receive data buses. programmable single/separate utopia clock via config1 register bit 23. 12.0 atm utopia interface cn8236 12.2 atm utopia interface logic atm servicesar plus with xbr traffic management 12-2 mindspeed technologies ? 28236-DSH-001-B 12.2 atm utopia interface logic the cn8236 atm utopia interface logic consists of the i/o drivers required to communicate with the external framer device, together with adaptation logic required to convert between either the utopia or slave utopia interface protocol, and the internal byte streams. configuration pins frcfg[1:0] and utopia1 determine whether the utopia or slave utopia protocol are used and whether it is level 1 or level 2. cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.3 atm physical i/o pins 28236-DSH-001-B mindspeed technologies ? 12-3 12.3 atm physical i/o pins the operational mode desired is indicated to the cn8236 by appropriately driving the frcfg[1:0] and utopia1 inputs according to tables 12-1 and 12-2 . table 12-1. atm physical interface mode select (frcfg[1:0]) frcfg[1:0] atm physical interface mode 0 0 reserved ? do not use 0 1 utopia 1 0 slave utopia 1 1 reserved ? do not use table 12-2. atm physical interface mode select (utopia1) utopia1 atm physical interface mode 0 utopia level 2 1 utopia level 1 12.0 atm utopia interface cn8236 12.3 atm physical i/o pins atm servicesar plus with xbr traffic management 12-4 mindspeed technologies ? 28236-DSH-001-B the interpretation of the atm utopia interface pins on the cn8236 and the actual signals generated or received by the framer in utopia mode are shown in table 12-3 . both the txclk and rxclk signals of the utopia interface can be derived from the clkd3 output of the cn8236. table 12-3. utopia mode signals cn8236 signal phy signal active polarity cn8236 direction txdata[15:0] txdata[15:0] ? out txpar txprty ? out txsoc txsoc high out txen* txenb* low out txclav txfull* low in txadd[4:0] txaddr[4:0] ? out txclk txclk rising edge in rxdata[15:0] rxdata[15:0] ? in rxpar rxprty ? in rxsoc rxsoc high in rxen* rxenb* low out rxclav rxempty* low in rxclk rxclk/txclk rising edge in rxadd[4:0] rxaddr[4:0] ? out cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.3 atm physical i/o pins 28236-DSH-001-B mindspeed technologies ? 12-5 the interpretation of the atm utopia interface pins on the cn8236 and the actual signals generated or received by the framer in slave utopia mode is shown in table 12-4 . table 12-4. slave utopia mode interface signals cn8236 signal phy signal active polarity cn8236 direction txdata[15:0] txdata[15:0] ? out txpar txprty ? out txsoc txsoc high out txen* txenb* low in txclav txemp* low out txclk txclk rising edge in rxdata[15:0] rxdata[15:0] ? in rxpar rxprty ? in rxsoc rxsoc high in rxen* rxenb* low in rxclav rxfull* low out rxclk rxclk rising edge in txaddr[4:0} txaddr[4:0} ? in rxaddr[4:0} rxaddr[4:0} ? in note: when operating the cn8236 in 8-bit mode, pull-ups need to be added to the unused high order bits (rxdata[15:8]). 12.0 atm utopia interface cn8236 12.3 atm physical i/o pins atm servicesar plus with xbr traffic management 12-6 mindspeed technologies ? 28236-DSH-001-B 12.3.1 utopia interface in addition to the current utopia level 1 support, this interface provides complete support for utopia level 2, 8/16 bit mode in both master and slave modes, including support for multi-phy in both master and slave modes. multi-phy port shaping is provided by tunnels through one txfifo buffer. a 3-bit port_id is used to provide port identification for up to 8 ports in master mode (utopia address 0 through 7) and 32 ports in slave mode. the utopia output drives are 8 ma to meet the multi-phy specification. multi-phy mode is enabled by setting config1(multi_phy) to a logic high. in master mode, the port_id field is used as a port identification. on the segmentation side, the appropriate port identification is written in the port_id field in the vcc table entry. the maximum allowable port_id is config1(num_ports). on the reassembly side, the utopia interface polls addresses 0 through config1(num_ports) for a cell. when a cell is detected in a phy, the cell along with the port_id is transferred to the reassembly block. an expanded lookup mechanism is used to find the appropriate state table entry. (see section 5.2.2.5 for more details.) in slave mode, the utopia block responds only when the utopia address equals config1(slave_addr). in non-multi-phy master mode, config1(slave_addr) is output on the rxaddr and txaddr busses. also, routing tag prepending is supported with programmable cell size up to 64 bytes in single phy master mode and single/multi-phy slave mode. on the reassembly side, the tag is discarded by the utopia interface. when f4 pmoam operation or vp abr operation is enabled, the routing tag content of all cells including oam within the vp must be identical. cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.4 utopia level 2 interface 28236-DSH-001-B mindspeed technologies ? 12-7 12.4 utopia level 2 interface the cn8236 supports both utopia level 1 and level 2 interfaces. these are described in general terms below with an emphasis on their differences. utopia level 1: this is an 8- or 16-bit interface designed for data rates up to 200 mbps at a clock rate of 25 mhz. both octet-level and cell level handshaking are supported. utopia level 2: this interface defines the multi-port support features that allow up to 31 utopia devices to multiplex on one utopia bus. the sar only supports up to eight phy devices. it allows either 8 or 16 bit data buses and uses only cell level handshaking. it can transfer up to 800 mbps when running at 50 mhz in the 16 bit mode. both level 1 and level 2 support odd parity over the width of the data bus. 12.4.1 cell tagging in addition to the standard 53-octet cell formats, given in tables 12-5 and 12-6 , the cn8236 supports user programmable cell sizes for routing tag applications. this allows a maximum cell size of 64 bytes. these cell formats are shown in tables 12-7 and 12-8 . the number of octets added for the tagging function is programmed into the tag_size bits of config1. table 12-5. cell format 8 bit mode bit 7 ... 0 header 1 header 2 header 3 header 4 udf1 (hec) (byte 5) payload 1 : payload 48 12.0 atm utopia interface cn8236 12.4 utopia level 2 interface atm servicesar plus with xbr traffic management 12-8 mindspeed technologies ? 28236-DSH-001-B table 12-6. cell format 16 bit mode bit 15 ... bit 8 bit 7 ... 0 header 1 header 2 header 3 header 4 udf1 (hec) (byte 5) udf2 (0) (byte 6) payload 1 payload 2 ... ... payload 47 payload 48 table 12-7. cell format, tagging enabled, 8 bit mode 70 tag 1 1 st byte of cell ... ... tag n header 1 header 2 header 3 header 4 hec payload 1 payload 2 ... ... ... payload 48 last byte of cell cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.4 utopia level 2 interface 28236-DSH-001-B mindspeed technologies ? 12-9 12.4.2 utopia configuration control most options for the cn8236 utopia interface are configured by control bits in the config0 and config1 registers. however, the selection of utopia level 1 versus level 2 and of master or slave mode is controlled by the input pins frcfg0, frcfg1, and utopia1. normally, these inputs are hardwired as required by the system design. utopia level 1/level 2: tying the utopia1 input pin to ground selects utopia level 2, connecting it to +3.3v selects utopia level 1. when selecting utopia level 2 be sure to program the utopia_mode bit to logic high to enable cell level handshaking (octet level handshaking is not valid in utopia level 2). master/slave selection: controlled by hardware inputs frcfg[1:0] as defined in table 12-1 . octet or cell handshaking: this is controlled by the utopia_mode bit in the config0 register. setting this bit high selects cell-level handshaking. in this mode, both the cn8236 and the selected port only begin a transfer when there is room in the fifo buffers for an entire cell. when utopia level 2 mode is selected, this bit must be set to logic high. utopia clocks: in the default state after a reset, the utopia transmit and receive blocks both use the rxclk input. by setting the multi_clk bit of config1 to logic high, the transmit side uses the txclk input. the utopia receive block continues to use the rxclk. multi-port operations: by default, the cn8236 expects a single device on the utopia bus. by setting the multi_phy bit of config1 to logic high, up to 8 devices can share the bus. utopia data bus width: the width of the utopia data bus is selectable by the utop16 bit of the config1 register. setting this bit high enables a 16-bit data path. table 12-8. cell format, tagging enabled, 16 bit mode 15 8 70 tag 1 tag 2 1 st word of cell ... ... ... ... tag n-1 tag n-2 header 1 header 2 header 3 header 4 hec not used payload 1 payload 2 ... ... ... ... payload 47 payload 48 last word of cell 12.0 atm utopia interface cn8236 12.4 utopia level 2 interface atm servicesar plus with xbr traffic management 12-10 mindspeed technologies ? 28236-DSH-001-B note: number of ports on the bus: when running in multi-port mode the total number of ports to poll is programmed into the num_ports bits of config1. since port numbering begins with 0, this value equals ? 1 (total number of ports). slave address: when the cn8236 is configured as a slave on the utopia bus, its port address must be programmed into the slave_addr bits of config1. software must be aware that all cn8236s on the bus default to the same address, (00), and therefore, must reprogram each device to a unique value. 12.4.3 utopia level 2 multi-port operation the cn8236 supports multi-port (up to eight) operations as described in the utopia level 2 specification af-phy-0039.000 (see the atm forum web site for details: www.atmforum.com ). two primary functions are involved in transferring data on the utopia bus: polling the ports to determine which ones have data ready and then selecting which port transfers its data. the receive side is discussed below. refer to the above referenced web page for more details. the cn8236 starts by polling port 0 and continue to num_ports as stored in the config1 register. polling is accomplished by outputting the desired port number on the utopia address bus. if that port has data ready it asserts the rxclav line. the controller can ignore this line and continue polling other ports or it can initiate the data transfer by holding the port address on the address lines while rxenb* is deasserted. once the data transfer has begun, the cn8236 can continue polling other ports. the polling and selection process waveforms are shown in figure 12-1 . this diagram assumes that 8 ports are present. at clock cycle a, port 5 has just been polled. it asserts the rxclav line to indicate that it has a complete cell to send. the cn8236 continues to poll ports 6 and 7 (both indicate that they do not have cells at this time). during this entire polling operation, data is being transferred across the data bus. at clock cycle b, the cn8236 has again output port 5 on the utopia address bus but this time has raised the txenb* line. this selects port 5. port 5 acknowledges that it is ready by again asserting rxclav. port 5 then asserts the rxsoc line and begins to transfer data. cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.4 utopia level 2 interface 28236-DSH-001-B mindspeed technologies ? 12-11 figure 12-1. utopia level 2 receive timing 1f 4 4 1f 5 55 1f 6 6 1f 7 7 1f 5 1f 0 1f rxclk rxaddr rxclav rxenb* rxdata rxsoc 40 41 42 43 44 45 46 47 h1 h2 h3 48 ab 8236_070 12.0 atm utopia interface cn8236 12.5 utopia level 1 mode cell handshake timing atm servicesar plus with xbr traffic management 12-12 mindspeed technologies ? 28236-DSH-001-B 12.5 utopia level 1 mode cell handshake timing if high, the utopia_mode bit in the config0 register selects cell-level handshaking. received data is latched from the rxdata[15:0] and rxpar lines on the rising edge of rxclk after rxen* is sampled active (see figure 12-2 ). the odd parity computed over the rxdata[15:0] lines is compared to the rxpar input. if in error, the fr_par_err bit is set in the host_istat0/ lp_istat0 registers. data is discarded upon a parity error if the rsm_phalt bit in the rsm_ctrl register is set to a logic high, and the reassembly coprocessor halts. the rxsoc signals to the cn8236 the start of cell. the rxclav input is the physical layer fifo buffer empty signal. when it is active, a complete cell is not present in the physical receive fifo buffer. the physical layer device sets rxclav inactive when it has a complete cell to transfer. the cn8236 sets rxen* to a logic low if it can accept a complete cell. on the clock cycle after the last octet of a cell is transferred, the cn8236 samples the rxclav input. if low, the physical device does not have a cell to transfer. if rxclav is high, the physical device has another cell to transfer and the cn8236 immediately starts receiving the next cell if it can accept a complete cell. the fr_rmode bit in the config0 register should be set to a logic low in this mode. figure 12-2. receive timing in utopia level 1 mode with cell handshake h1 *** p47 p48 x h2 h1 *** p47 p48 rxclk rxsoc rxclav rxen* rxd/rxpar (2) (1) (3) 8236_071 note(s): (1) once a cell transfer is started, rxclav is not sampled until the end of the cell. (2) rxen* goes active only if there is room in the fifo buffer for a complete cell. (3) rxen* goes inactive at cell boundaries if the receive fifo buffer cannot accept another cell. cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.5 utopia level 1 mode cell handshake timing 28236-DSH-001-B mindspeed technologies ? 12-13 transmit data is driven on txdata[15:0] on the rising edge of txclk when txen* is asserted. txen* is only asserted when there is data in the cn8236 transmit fifo buffer. simultaneously, the odd parity computed over the txdata[15:0] lines is driven on to the txpar output. the txsoc line is driven by the framer device to indicate start of cell. if the txclav input is asserted by the framer device, the framer device is full, and another cell is not transmitted to the physical framer. (see figure 12-3 .) in utopia mode, the txclk input can be connected to the cn8236 clkd3 output; a 50% duty cycle clock derived by dividing clk2x by three. figure 12-3. transmit timing in utopia level 1 mode with cell handshake h1 *** p44 p45 p46 p47 p48 x h1 *** p48 x txclk txsoc txclav txen* txd/txpar (2) (1) (3) (4) 8236_072 note(s): (1) once transfer of a cell is started, txclav is sampled only on the last octet of a cell. (2) txen* goes active if txclav is inactive at previous rising clock edge and a complete cell in the transmit fifo buffer. (3) txen* goes inactive due to txclav being active on previous cycle. (4) txen* goes inactive since a complete cell is not in the transmit fifo buffer. 12.0 atm utopia interface cn8236 12.6 utopia level 1 mode octet handshake timing atm servicesar plus with xbr traffic management 12-14 mindspeed technologies ? 28236-DSH-001-B 12.6 utopia level 1 mode octet handshake timing if low, the utopia_mode bit in the config0 register selects octet-level handshaking. received data is latched from the rxdata[15:0] and rxpar lines on the rising edge of rxclk after rxen* is sampled active (see figure 12-4 ). the odd parity computed over the rxdata[15:0] lines is compared to the rxpar input. if in error, fr_par_err in the host_istat0/lp_istat0 registers is set. data is discarded upon a parity if the rsm_phalt bit in the rsm_ctrl register is set to a logic high, and the reassembly coprocessor halts. the rxsoc signals the start of cell to the cn8236. the rxclav input is the physical layer fifo buffer empty signal. when it is active, no data is present in the physical receive fifo buffer. the physical layer device sets rxclav inactive when it has an octet to transfer. the cn8236 sets rxen* to a logic low if it can accept an octet in the next clock cycle. the fr_rmode bit in the config0 register should be set to a logic low in this mode. figure 12-4. receive timing in utopia level 1 mode with octet handshake h1 h2 h3 x h4 x h5 *** p48 h1 h2 h3 rxclk rxsoc rxclav rxen* rxd/rxpar (1) 8236_073 note(s): (1) rxen* goes inactive only if there is no room for another octet in the receive fifo buffer. cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.6 utopia level 1 mode octet handshake timing 28236-DSH-001-B mindspeed technologies ? 12-15 transmit data is driven on txdata[15:0] on the rising edge of txclk when txen* is asserted. txen* is only asserted when there is data in the cn8236 transmit fifo buffer. simultaneously, odd parity computed over the txdata[15:0] lines is driven on to the txpar output. the txsoc line is driven by the framer device to indicate start of cell. if the txclav input is asserted by the framer device, the framer device is full and can accept only one to four more octets. (see figure 12-5 .) in utopia mode, the txclk input can be connected to the cn8236 clkd3 output, which is a 50% duty cycle clock derived by dividing the clk2x input by three. figure 12-5. transmit timing in utopia level 1 mode with octet handshake h1 *** p45 p46 p47 x p44 x p48 x h1 h2 txclk txclav txen* txd/txpar (1) (2) 8236_074 note(s): (1) txen* goes active of txclav is inactive at previous rising clock edge and a complete cell in the transmit fifo buffer. (2) txen* goes inactive one to four clock cycles after txclav goes active. txsoc 12.0 atm utopia interface cn8236 12.7 slave level 1 utopia mode atm servicesar plus with xbr traffic management 12-16 mindspeed technologies ? 28236-DSH-001-B 12.7 slave level 1 utopia mode the slave utopia mode is similar to the utopia mode, except the direction of the enable signals and fifo buffer flags are reversed. this allows a switch fabric or backplane to directly control the physical port. the transmit and receive enable signals are generated by the physical layer instead of the cn8236. the txfull* signal is changed to the txempty* signal and is an output of the cn8236. the rxempty* signal is changed to the rxfull* signal, and is also an output of the cn8236. this mode supports only a cell-level handshake protocol. received data is latched from the rxdata[15:0] and rxpar lines on the rising edge of rxclk when rxen* is active (see figure 12-6 ). the odd parity computed over the rxdata[15:0] lines is compared to the rxpar input. if there is a parity error, the fr_par_err bit is set in the host_istat0/lp_istat0 registers. data is discarded upon a parity error if the rsm_phalt bit in the rsm_ctrl register is set to a logic high. if so, the reassembly coprocessor halts upon a parity error. the rxsoc signals to the cn8236 the start of cell. the rxclav output is the receive fifo buffer full signal. when it is active, the cn8236 cannot accept another cell. the cn8236 sets rxclav inactive when it has room in the receive fifo buffer for another cell. the physical device sets rxen* to a logic low if it can transfer an octet. the fr_rmode bit in the config0 register should be set to a logic low in this mode. figure 12-6. receive timing in slave utopia level 1 mode h2 h3 p44 *** p48 x h1 h2 rxclk rxsoc rxclav rxen* rxd/rxpar (1) (2) (3) p47 p46 p45 x h1 x 8236_075 note(s): (1) rxclav goes inactive when there is room in the receive fifo buffer for a complete cell. (2) rxclav goes active when there is no longer room in the receive fifo buffer for another complete cell. (3) rxen* need not be inactive when rxclav is active. cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.7 slave level 1 utopia mode 28236-DSH-001-B mindspeed technologies ? 12-17 transmit data is driven on txdata[15:0] on the rising edge of txclk after txen* is sampled asserted. simultaneously, the 8-bit odd parity computed over the txdata[15:0] lines is driven on to the txpar output. the txsoc line is driven by the sar to indicate start of cell. if the txclav output is asserted by the cn8236, the transmit fifo buffer does not contain a complete cell. (see figure 12-7 .) figure 12-7. transmit timing in slave utopia level 1 mode h5 p1 p2 *** *** txclk txsoc (txmark) txclav (txflag*) txen* txd/txpar (1) (4) (3) (3) (2) 8236_076 note(s): (1) txclav goes active when a complete cell is in the transmit fifo buffer. (2) example of physical device deactivating txen*. (3) the txd/txpar and txsoc lines are three-stated (floated) when txen* is sampled high (de-asserted). (4) physical device can keep txen* active while txclav is inactive. h1 p3 h2 h1 p48 12.0 atm utopia interface cn8236 12.8 loopback mode atm servicesar plus with xbr traffic management 12-18 mindspeed technologies ? 28236-DSH-001-B 12.8 loopback mode the physical interface can be internally looped by setting the fr_loop bit in the config0 register to a logic high. this mode uses the internal system clock for operation; therefore, a framer clock is not needed during loopback operation. when the fr_src_loop signal equals 1, the interface loops back the data and control signals so the path from the segmentation coprocessor to the reassembly coprocessor can be tested. the internal connections of the phy device interface signals are connected, as figure 12-8 illustrates. the transmit side is put into the utopia mode and the receive side is put into the reverse utopia mode. in this mode, the outputs of the chip, txdata, txpar, txsoc, txen*, and rxclav are three-stated, so there are no output conflicts with other devices connected to these signals. note: a reset of the reassembly coprocessor is required after the changing of the fr_loop bit, because this changes the source of the clock to the physical interface circuitry. to accomplish this reset, assert rsm_ctrl0 (rsm_reset). figure 12-8. source loopback mode diagram transmit side in utopia mode receive side in reverse utopia mode sysclk txd[15:0] txpar txsoc txen* txclav txaddr[4:0] rxd[15:0] rxpar rxsoc rxen* rxclav rxaddr[4:0] 8236_077 cn8236 12.0 atm utopia interface atm servicesar plus with xbr traffic management 12.9 receive cell synchronization logic 28236-DSH-001-B mindspeed technologies ? 12-19 12.9 receive cell synchronization logic the receive cell synchronization logic accepts a stream of octets (together with error and cell boundary indications) from the receive atm utopia interface and performs the following functions: maintains a sequence counter that marks the various components of an atm cell: the 5-byte atm header, the 1-byte hec field within the header, and the 48-byte payload. the sequence counter is also used by the atm utopia interface to check cell boundary synchronization. extracts and discards the hec byte from each 53-byte atm cell, leaving 52 bytes of cell data. formats consecutive 4-byte segments into 32-bit words; thus, the header forms the first word, the first four bytes of the payload form the next word, and so on. a total of thirteen 32-bit words are created from each 52-byte cell after the hec byte has been removed. the bytes within each word are left-justified (big-endian format), that is, the first byte received is the msb of the word. ensures that a complete cell (exactly 52 bytes) is always written to the fifo buffer. if a synchronization error occurs, the fr_sync_err bit in the host_istat0/lp_istat0 registers is set. the atm utopia interface attempts to re-synchronize with the data stream. sets the rsm_ovfl bit in the host_istat0/lp_istat0 registers if an octet could not be transferred due to the receive fifo buffer being full. 12.0 atm utopia interface cn8236 12.10 transmit cell synchronization logic atm servicesar plus with xbr traffic management 12-20 mindspeed technologies ? 28236-DSH-001-B 12.10 transmit cell synchronization logic the transmit cell synchronization logic copies cell data from the transmit cell fifo buffer to the transmit atm utopia interface while performing the following functions: reads 32-bit words from the transmit cell fifo buffer and converts them to a stream of octets, with the msb of each 32-bit word corresponding to the first byte derived from that word (big-endian format). maintains a sequence counter that delineates the various components of each atm cell (4-byte header, 48-byte payload) in the outgoing byte stream. inserts a blank (all-0) hec byte, used as a placeholder, into the outgoing byte stream representing each atm cell. the hec placeholder is inserted after the first four bytes (the atm header) have been transferred. generates appropriate cell delineation pulses to the transmit atm utopia interface logic, for use in generating the txsoc output, and also in verifying synchronization with the framer device. if the atm physical transmit interface runs out of cells to transmit, the device sets the seg_unfl bit in the host_istat0/lp_istat0 registers. the transmit cell synchronization logic supplies a continuous stream of octets to the transmit atm utopia interface unit, with cell delineation pulses at the starting byte of every cell. only complete 53-byte cells are supplied to the atm utopia interface. if the transmit cell fifo buffer is empty, the transmit cell synchronization logic indicates that no more data can be transferred to the framer. 28236-DSH-001-B mindspeed technologies ? 13-1 13 13.0 aalx interworking the aalx is a programmable platform that supports development of various voice processing algorithms. header processing is required since the cells from various channels are streamed to or from one fifo buffer in the aalx. the function of the sar is to integrate aalx and host processor traffic (that is, management) and to provide traffic shaping in network centric scheduling applications. this solution supports up to six aalx parts. pci masters communicate with aalxs through either a fifo buffer or mailbox registers. in order for the sar to communicate with the aalx fifo buffer, the rsm and seg need to be configured in 52-octet logical fifo buffer mode, and the fifo buffer on the aalx must be in slave access mode. on the ingress side, the rsm block performs atm header lookup on each cell and steers the voice data cells to the appropriate aalx. in addition, it determines the state of the aalx ingress fifo buffer and drop cells if full. on the egress side, the seg block supports two scheduling modes, network centric scheduling and voice centric scheduling. in network centric scheduling, the scheduling table can be locked to the network cell rate. cbr entries are written for each aalx. when a transmit opportunity is detected, the seg block determines the state of the appropriate aalx egress fifo buffer and retrieves a cell if available. in voice centric scheduling, the seg block constantly determines the state of each aalx egress fifo buffer and retrieves and transmits a cell as soon as one is available. the transmission of a cell bumps management cells scheduled by the sar. to better support network-centric scheduling, an external scheduler reference clock is supplied. in addition, the phys add a cell slot reference output clock. in order for the rsm to determine the state of the aalx ingress fifo buffer, the aalx toggles a gpio output every time it reads a cell from the fifo buffer. this output is connected to the hfifordx input of the sar. the rsm block maintains a shadow fifo buffer read counter and can determine if there is room to accept another cell. similarly, the aalx toggles another gpio output every time it writes a cell to the egress fifo buffer. this output is connected to the hfifowrx input. the seg maintains a shadow fifo buffer write counter to determine that a cell is available. the ingress and egress fifo buffer shadow counters have a programmable fifo buffer depth up to 16 cells via the aalx_ctrl register. 13.0 aalx interworking cn8236 atm servicesar plus with xbr traffic management 13-2 mindspeed technologies ? 28236-DSH-001-B the header word of each contains the vcc_index of the channel. the format of the word is as follows in tables 13-1 and 13-2 : seg: reserved (12 bits) | seg_vcc_index (16) | pti (3) | clp (1) rsm: rsm_route_tag (28) | pti (3) | clp (1) on reassembly, the vpi and vci are stripped from the atm header word, and the rsm_route_tag is added. this eliminates the need for a lookup algorithm in the aalx and still allows the aalx to perform aal5 processing since the pti field is passed. on the segmentation side, the same header word is passed from the aalx to the sar. the seg block can use the vcc_index to determine the routing tag and also to support pm-oam in the future. the pti field is passed to the cell without change; however, the clp bit is ored with the clp bit in the atm header field of the vcc table entry. in order to generate management traffic and to configure the aalx pci registers, a central pci resource is required. this consists of a processor and central pci bridge chip. note: pm-oam operation does not work with this configuration. table 13-1. seg_vcc_index format table word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved seg_vcc_index pti clp table 13-2. rsm_route_tag format table word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 rsm_route_tag pti clp cn8236 13.0 aalx interworking atm servicesar plus with xbr traffic management 13.1 aalx rsm operation 28236-DSH-001-B mindspeed technologies ? 13-3 13.1 aalx rsm operation to support aalx operation, hport_id and aalx_en are added to the reassembly vcc table entry as follows: aalx_en is added to bit 21 of word 0. when this bit is set high, the dpri field is used as the hport_id. for proper operation with the aalx part, the channel must be set up per logical fifo buffer mode (fifo_en = 1), that is, aal0 fixed termination mode with termination length of one cell. also, m52_en must be a logic high. in addition, a rsm_route_tag is written into the upper 28 bits of the bom_bd_pntr word on the rsm vcc table entry. six shadow fifo buffer counters, corresponding to each hfifordx input, is maintained. when the ingress fifo buffer is written, the counter is incremented. an edge detection circuit decrements each counter. the counter size is programmable via the aalx_ctrl(ingress_depth) register up to 16 cells. each counter is reset by either rsm_reset or a separate reset per port. when a write occurs on a full condition, hrsmovflx output pulses to a logic high for one clock period. when a read occurs on an empty condition, hrsmunflx output pulses to a logic high for one clock period. rollover or rollunder of the counter must be prevented. when a cell is received, the normal cell lookup process occurs. if aalx_en is active in the vcc table entry, dpri is used as the hport_id. the rsm block checks if room is available in the appropriate aalx fifo buffer. if so, the fifo buffer address in the vcc table entry is used to transfer the complete cell (52 octet mode). if not, the cell is discarded. the atm header word is modified to pass the rsm_route_tag as follows: rsm_route_tag (28 bits) | pti (3) | clp (1). 13.0 aalx interworking cn8236 13.2 aalx seg operation atm servicesar plus with xbr traffic management 13-4 mindspeed technologies ? 28236-DSH-001-B 13.2 aalx seg operation to support aalx operation, hport_id and aalx_en are added to the segmentation vcc table entry as follows: aalx_en is added to bit 21 of word 5 and hport_id is added to word 5 (of a cbr mode connection) bits 26 through 30. hport_id is only used in network centric scheduling (that is, external_sch = 0). (the pci addresses for each aalx are stored in internal memory as shown in table 4-6 .) six shadow fifo buffer counters, corresponding to each hfifowrx input, are maintained. an edge detection circuit increments each counter. the counter is decremented after a read of the cell. a non 0 count indicates a cell is available for transmit from the corresponding aalx. the counter size is programmable up to 16 cells via the aalx_ctrl(egress_depth) register. each counter is reset by either seg_reset or a separate reset per port. when a write occurs on a full condition, hsegovflx output pulses to a logic high for one clock period. the counter should prevent rollover or roll-under. 13.2.1 aalx network centric operation ? (external_sch = 0) in this mode, the aalx traffic stream is scheduled using a cbr connection, with bandwidth reserved in the schedule table. the segmentation block, processing a cbr connection from the scheduler with aalx_en set high, looks up the hport_id field to identify which hfifowrx counter check to determine if a cell is available from that aalx. if it is, the pci address for that aalx is looked up from the corresponding internal memory address and the entire cell (52 bytes) with modified atm header word is read across the pci bus. this process is similar to the virtual fifo buffer scheduling mode as exists today. however, no rate matching using the sch_opt bit is required, the curr_pntr field is a don ? t care, and the header is included in the cell read across the pci bus, as opposed to being read from the vcc table. to set up a connection for the aalx traffic stream in this mode, the user does the following: populates the schedule table with the connection ? s vcc index. sets the connection ? s vcc table entries: aalx_en = 1, hport_id, and sch_mode = cbr. writes the aalx ? s fifo buffer pci address to internal memory. writes the atm header into vcc entry. to enable the aalx traffic stream to be transmitted, sets the connection ? s vcc table run bit high. cn8236 13.0 aalx interworking atm servicesar plus with xbr traffic management 13.2 aalx seg operation 28236-DSH-001-B mindspeed technologies ? 13-5 13.2.2 aalx voice centric operation ? (external_sch = 1) no scheduling is performed by the scheduler block in this mode. for each processing loop through its state machine, the segmentation block monitors the cell-available counters (priority is round-robin) to determine if any have data available for transmission. if so, the pci address for the corresponding aalx is looked up from internal memory, and the entire cell (52 bytes) with modified atm header word is read across the pci bus. no connection setup is required in this mode; the user must do the following: write the aalx ? s fifo buffer pci address to internal memory. write atm header into vcc entry. the aalx traffic stream is enabled as the aalx strobes hfifowrx. 13.0 aalx interworking cn8236 13.2 aalx seg operation atm servicesar plus with xbr traffic management 13-6 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? 14-1 14.0 cn8236 registers 14.1 control and status registers each cn8236 register description is prefaced with the appropriate abbreviated access types described in table 14-1 . detailed control and status register (csr) descriptions are listed in table 14-2 . note: the byte-enables are ignored by the cn8236 when writing to control and status registers. the access type terminology given in table 14-1 applies to all registers in this section. table 14-1. type abbreviation description abbreviation description r/w read and write access for both host and local processors r/w h read and write access for host; read only access for local processor r/w l read and write access for local; read only access for host processor r/w r read and write access for both processors with restrictions r/o-w/o b part of this register is read only; part write only by both processors r/o read only access for both processors 14 14.0 cn8236 registers cn8236 14.1 control and status registers atm servicesar plus with xbr traffic management 14-2 mindspeed technologies ? 28236-DSH-001-B register terminology table 14-2. cn8236 control and status registers (1 of 2) address name type description 0x00 clock r/w real time clock register 0x04 alarm1 r/w alarm register 1 0x08 reserved ? not implemented 0x0c sys_stat r/o system status register 0x10 reserved ? not implemented 0x14 config0 r/w basic configuration and control register 0 0x18 config1 r/w basic configuration and control register 1 0x1c int_delay r/w interrupt delay register 0x20 aalx_ctrl r/w aalx control register 0x24 ? 0x7c reserved ? not implemented 0x80 seg_ctrl r/w segmentation control register 0x84 seg_vbase r/w seg vcc table and schedule table base address register 0x88 seg_pmbase r/w seg pm table and bucket table base address register 0x8c seg_txbase r/w segmentation transmit queue base register 0x90 seg_tagbase r/w base address of routing tag table 0x94 ? 0x9c reserved ? not implemented 0xa0 sch_pri r/wb schedule priority queue control register 1 0xa4 sch_pri_2 r/w schedule priority queue control register 2 0xa8 sch_size r/w schedule size and slot minimum drain rate register 0xac sch_ctrl r/w scheduler control register 0xb0 sch_abr_max r/w maximum abr vcc_index register 0xb4 sch_abr_con r/w schedule abr constant register 0xb8 sch_abrbase r/w abr decision table lookup base register 0xbc sch_cng r/w abr congestion notification register 0xc0 pcr_que_int01 r/w pcr queue interval 0 and 1 register 0xc4 pcr_que_int23 r/w pcr queue interval 2 and 3 register 0xc8 ? 0xec reserved ? not implemented 0xf0 rsm_ctrl0 r/w reassembly control register 0 0xf4 rsm_ctrl1 r/w reassembly control register 1 0xf8 rsm_fqbase r/w reassembly free buffer queue base register 0xfc rsm_fqctrl r/w reassembly free buffer queue control register 0x100 rsm_tbase r/w reassembly table base register cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.1 control and status registers 28236-DSH-001-B mindspeed technologies ? 14-3 0x104 rsm_to r/w reassembly time-out register 0x108 rs_qbase r/w reassembly/segmentation queue base register 0x10c ers_base r/w reassembly er_shift tables base register 0x110 vpi_size r/w variable vpi size register 0x114 tx_fifo_ctrl r/w transmit port register 0x118 tx_port_ctrl r/w transmit port control register 0x11c ? 0x15c reserved ? not implemented 0x160 cell_xmit_cnt r/o atm cells transmitted counter 0x164 cell_rcvd_cnt r/o atm cells received counter 0x168 cell_dsc_cnt r/o atm cells discarded counter 0x16c aal5_dsc_cnt r/o aal5 pdus discarded counter 0x170 ? 0x19c reserved ? not implemented 0x1a0 host_mbox r/w l host mailbox register 0x1a4 host_st_wr r/o host status write register 0x1a8 aalx_stat r/o aalx counter status register 0x1ac tx_status r/o tx port cell discard status register 0x1b0 lp_mbox r/w h local processor mailbox register 0x1b4 ? 0x1bc reserved ? not implemented 0x1c0 host_istat0 r/o host interrupt status register 0 0x1c4 host_istat1 r/o host interrupt status register 1 0x1c8 ? 0x1cc reserved ? not implemented 0x1d0 host_imask0 r/w h host interrupt mask register 0 0x1d4 host_imask1 r/w h host interrupt mask register 1 0x1d8 ? 0x1dc reserved ? not implemented 0x1e0 lp_istat0 r/o local processor interrupt status register 0 0x1e4 lp_istat1 r/o local processor interrupt status register 1 0x1e8 ? 0x1ec reserved ? not implemented 0x1f0 lp_imask0 r/w l local processor interrupt mask register 0 0x1f4 lp_imask1 r/w l local processor interrupt mask register 1 0x1f8 ? 0x1fc reserved ? not implemented table 14-2. cn8236 control and status registers (2 of 2) address name type description 14.0 cn8236 registers cn8236 14.2 system registers atm servicesar plus with xbr traffic management 14-4 mindspeed technologies ? 28236-DSH-001-B 14.2 system registers 0x00 ? real-time clock register (clock) this register contains the 32-bit real time clock. it is incremented by the system clock (sysclk), which has been divided by the divider[6:0] field in the config0 register. it can be written to any value by each processor, and can generate an interrupt on the rtc_ovfl status bit in the lp_istat0 register when it overflows from 0xffffffff to 0x0. 0x04 ? alarm register 1 (alarm1) this register contains a 32-bit value which is compared against the clock register. when the two registers are equal, the alarm1 status bit in the lp_istat0 register is latched and can be enabled to cause an interrupt to the local processor. to implement a periodic interrupt, add a constant value to this register after each interrupt. bit field size name description 31 ? 0 32 clock[31:0] real-time clock value. bit field size name description 31 ? 0 32 alarm1[31:0] alarm1 comparison value. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.2 system registers 28236-DSH-001-B mindspeed technologies ? 14-5 0x0c ? system status register (sys_stat) the system status register provides read-only system status. this register reflects the device id and version information for the part, and pin-programmable options that otherwise might not be visible to the processors. it also contains expanded information for the status located in the host_istat0 and lp_istat0 registers. bit field size name description 31 ? 17 15 reserved not implemented at this time. 16 ? 12 5 pci_bus_status [4:0] the status bits are as follows: 4 = target abort 3 = master abort 2 = parity error 1 = interface disabled 0 = internal failure reflects corresponding error bits in the pci configuration register. bits are reset by either a write to the pci configuration register by the host, or by setting config0 (pci_err_reset) bit. 11 1 rammode reflects the state of the rammode input pin. 10 1 procmode reflects the state of the procmode input pin. 9, 8 2 frcfg[1:0] reflects the state of the frcfg[1:0] input pins. 7 ? 4 4 version [3:0] version number for the cn8236: rev a = 0 and rev b = 2. 3 ? 0 4 device[3:0] device id for the cn8236; set to 4. 14.0 cn8236 registers cn8236 14.2 system registers atm servicesar plus with xbr traffic management 14-6 mindspeed technologies ? 28236-DSH-001-B 0x14 ? configuration register 0 (config0) this register provides all control and configuration bits that are not associated with the reassembly and segmentation coprocessors. the majority of these configuration bits are set at initialization time and are not changed dynamically. the assertion of the hrst* system reset pin clears all of the bits in the config0 register except for memctrl, which is set high. bit field size name description 31 1 lp_enable when set, this bit causes the prst* output pin to be high. this can be used to reset the local processor. 30 1 global_reset when set, this bit causes reset of the segmentation and reassembly coprocessors and all latched status. 29 1 pci_mstr_reset when set, this bit resets the pci master logic. once active, this bit must stay active for 16 cycles of the hclk input signal. 28 1 pci_err_reset when set, resets all pci error bits in the pci configuration, including rma, rta, dpr, intf_dis, int_fail, and merror. this also re-enables pci master operation. 27 1 reserved always set to 0. 26 1 8223_mode when set, enables modified microprocessor interface timing to phy. 25 1 phy2_en enables the second phy device memory space in standalone operation. 24 1 int_lbank when set, allows only byte 0 and 1 writes to address space 0x1000 ? 0x10ff and 0x1400 ? 0x14ff. this allows endian neutral access of the status queue base table read_ud field by the host or local processor. 23 1 pci_wr_rd when this bit is high, the pci master arbitration scheme is set to write priority over read. this bit takes precedence over pci_arb (bit 21). 22 1 pci_read_multi when this bit is set, the sar ? s pci master implements the pci read multiple command. otherwise, the pci master implements the pci read command. 21 1 pci_arb selects pci master arbitration scheme. when a logic high, enables round-robin between read and write requests. when a logic low, reads have priority over writes. 20 ? 16 5 statmode[4:0] selects which internal status to output on the stat[1:0] output pins. 15 1 fr_rmode (bt8222/3) controls reassembly start of cell processing. when set low, processing starts after the first two words of a cell are received. when set high, a complete cell must be in reassembly fifo buffer before cell is processed. 14 1 fr_loop when set, this bit enables loopback of cells at the atm physical interface. loopback uses sysclk. 13 1 utopia_mode selects byte or cell utopia handshake mode. 0 = octet handshake 1 = cell handshake 12 1 endian selects between little and big endian host data structures. 0 = little endian 1 = big endian cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.2 system registers 28236-DSH-001-B mindspeed technologies ? 14-7 0x18 ? configuration register 1 (config1) this register provides system control and configuration bits that are not directly associated with the reassembly and segmentation coprocessors. the majority of these bits are configuration bits (which occur at initialization time) and are not changed dynamically. the assertion of the hrst* system reset pin clears all bits in the config1 register for backward compatibility. 11 1 lp_bwait selects 0 or 1 wait states between consecutive data cycles during local processor burst accesses. set to logic low for standalone operation mode. 10 1 memctrl selects 0 or 1 wait states sar-shared memory (1- or 2-cycle). (1) 9 ? 7 3 banksize[2:0] selects size of memory banks for contiguous memory support. see section 9.2 , for further explanation. 6 ? 0 7 divider[6:0] pre-scaler for sysclk which advances the counter in the clock register . sysclk is divided by the divider value; if 0, divided by 128. note(s): (1) if 1 wait state is selected, pwait function does not work. bit field size name description bit field size name description 31 ? 24 8 reserved set to 0. 23 1 multi_clk if logic high, selects separate utopia transmit and receive clocks. if logic low, both clocks use the rxclk input. 22 1 multi_phy if logic high, multi-phy operation is enabled. 21 1 utop16 if logic high, utopia 16 bit interface is enabled; otherwise 8-bit interface. 20 ? 18 3 num_ports[2:0] number of phy ports to poll when in master utopia mode starting with address 0. number of ports = (num_ports + 1) 17 ? 13 5 slave_addr[4:0] when in slave utopia multi-phy mode, this is the utopia device address of the sar. when in master non-multi-phy mode, this is the address present on both txaddr and rxaddr. 12 ? 9 4 tag_size[3:0] select tag size. valid range is 0 to 11. in 16 bit mode (utop16 = 1), only even size tags are valid. 8 ? 4 5 phybank[4:0] physical chip bank select. this value is placed on laddr[13:9] when a phy1 or phy2 control access occurs. 3 1 reserved set to 0. 2 1 tx_fifo_flush_en enables tx_fifo_flush mechanism. this mechanism is valid only in utopia master and multi-phy modes. 1 1 incfifo_sz incoming dma fifo buffer size. logic high sets the fifo buffer to 8 kb, logic low to 2 kb. 0 1 new_pmoam when a logic high, the new_pmoam mechanism is enabled. 14.0 cn8236 registers cn8236 14.2 system registers atm servicesar plus with xbr traffic management 14-8 mindspeed technologies ? 28236-DSH-001-B 0x1c ? interrupt delay register (int_delay) 0x20 ? aalx control register (aalx_ctrl) bit field size name description 31 ? 11 21 reserved set to 0. 10 1 timer_loc if logic high, interrupt hold-off timer used with local interrupt; else with host interrupt. 9 1 en_timer enable status queue interrupt timer delay. 8 1 en_stat_cnt enable status queue interrupt counter delay. 7 ? 0 8 stat_cnt[7:0] number of status queue entries written before allowing interrupt to propagate to output pin. bit field size name description 31 ? 30 2 reserved set to 0. 29 ? 24 6 rst_ingress_fifo [5:0] if logic high, resets the aalx ingress fifo buffer shadow counter. 23 ? 22 2 reserved set to 0. 21 ? 16 6 rst_egress_fifo [5:0] if logic high, resets the aalx egress fifo buffer shadow counter. 15-12 4 reserved set to 0. 11 ? 8 4 ingress_depth depth of all ingress fifo buffers in terms of number of cells. actual depth = register value +1. 7 ? 4 4 reserved set to 0. 3 ? 0 4 egress_depth depth of all egress fifo buffers in terms of number of cells. actual depth = register value +1. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.3 segmentation registers 28236-DSH-001-B mindspeed technologies ? 14-9 14.3 segmentation registers 0x80 ? segmentation control register (seg_ctrl) this register contains general control bits for the segmentation coprocessor. the assertion of the hrst* system reset pin or global_reset bit in the config0 register causes the clearing of the seg_enable control bit. bit field size name description 31 1 seg_enable segmentation enable ? enables segmentation coprocessor. if disabled, the segmentation coprocessor halts on a cell boundary. 30 1 seg_reset segmentation reset ? resets segmentation coprocessor and pointers. 29 ? 27 3 vbr_offset offset from schedule slot priority to general priority. (vbr_offset+(#vbr / abr priorities) 7.) not active if use_sch_ctrl is asserted. 26 1 seg_gfc enable segmentation gfc processing. the segmentation machine is disabled when the sar receives cells with gfc halt set. gfc priority queues (set in the sch_pri register) are active for one cell for each received cell with gfc set_a bit = 1. 25 1 dbl_slot each schedule slot occupies two words. not active if use_sch_ctrl is asserted. 24 1 cbr_tun use first entry in each schedule slot for cbr/tunnel traffic. 23 1 adv_abr_tmplt advanced abr template mode. when logic high, per-connection mcr and icr enabled. when logic low, per-template mcr and icr enabled. 22 1 use_sch_ctrl activate the use of slot_depth, the 4-bit vbr_offset field, and tun_pri0_offset from the sch_ctrl register. deactivate the use of dbl_slot and the 3-bit vbr_offset field from the seg_ctrl register. this bit cannot be set to a logic high in 8235 mode. 21 ? 16 6 reserved program and read as 0. 15 ? 12 4 tx_fifo_len depth of transmit fifo buffer in cells. valid range is 3 ? 9. to ensure optimum performance, the depth of the fifo buffer should be at least three. 11 1 clp0_eom set clp in atm header to 0 on last cell of cpcs-pdu. 10 ? 6 5 oam_stat_id status queue id for buffer descriptors with oam_stat set. 5 1 seg_st_halt enables a status queue entry for a vcc halted with a partially segmented packet. 4 1 seg_ls_dis segmentation local status disable ? disable segmentation check for sar-shared memory status queue full condition. if this bit is not set, the segmentation coprocessor does not segment any cells for a vcc assigned to a full sar-shared memory status queue. this bit can be used to disable overflow checking when the queues are sized large enough to prevent overflow. 14.0 cn8236 registers cn8236 14.3 segmentation registers atm servicesar plus with xbr traffic management 14-10 mindspeed technologies ? 28236-DSH-001-B 0x84 ? segmentation vcc table and schedule table base address register (seg_vbase) the seg_vbase register sets the base address in sar-shared memory for the segmentation vcc table and the schedule table. both base addresses are 128-byte aligned, and only the 16 most significant bits of the address are specified in the seg_vbase register. 0x88 ? segmentation pm base register (seg_pmbase) the seg_pmbase register sets the base address in sar-shared memory for the vbr bucket table and the performance monitoring table. both base addresses are 128-byte aligned, and only the 16 most significant bits of the address are specified in the seg_pmbase register. 3 1 seg_hs_dis segmentation host status disable ? disable segmentation check for pci memory status queue full condition. if this bit is not set, the segmentation coprocessor does not segment any cells for a vcc assigned to a full pci memory status queue. this bit can be used to disable overflow checking when the queues are sized large enough to prevent overflow. 2 1 tx_rnd set for transmit queue servicing in round-robin order. clear for transmit queue servicing in priority order (31 is highest priority). 1-0 2 tr_size[1:0] number of entries in each transmit queue. 00 = 64 01 = 256 10 = 1,024 11 = 4,096 bit field size name description bit field size name description 31 ? 16 16 seg_schb[15:0] base address for the schedule table. 15 ? 0 16 seg_vccb[15:0] base address for the segmentation vcc table. bit field size name description 31 ? 16 16 seg_bckb[15:0] base address for the vbr bucket table. (see section 6.2.4.4 , for details on loading bucket table entries.) 15 ? 0 16 seg_pmb[15:0] base address for the performance monitoring table. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.3 segmentation registers 28236-DSH-001-B mindspeed technologies ? 14-11 0x8c ? segmentation transmit queue base register (seg_txbase) the seg_txbase register sets the base address in sar-shared memory for the transmit queues and enables the individual queues. the base address is 128-byte aligned and only the 16 most significant bits of the address are specified in the seg_txbase register. 0x90 ? segmentation routing tag table base register (seg_tagbase) bit field size name description 31 ? 16 16 seg_txb[15:0] base address for the transmit queues. 15 ? 13 3 reserved program and read as 0. 12 ? 5 8 xmit_interval[7:0] interval for transmit queue read_ud_pntr update. 4 ? 0 5 tx_en transmit queues 0-tx_en are enabled. bit field size name description 31 ? 16 16 reserved always set to 0. 15 ? 0 16 seg_tagb[15:0] base address for the routing tag table. 14.0 cn8236 registers cn8236 14.4 scheduler registers atm servicesar plus with xbr traffic management 14-12 mindspeed technologies ? 28236-DSH-001-B 14.4 scheduler registers 0xa0 ? schedule priority register (sch_pri) this register specifies the use of each global priority pointer for priority queues 0 through 7. bit field size name description 31 1 qpcr_ena7 enable pcr limits on global priority pointer 7. 30 1 qpcr_ena6 enable pcr limits on global priority pointer 6. 29 1 qpcr_ena5 enable pcr limits on global priority pointer 5. 28 1 qpcr_ena4 enable pcr limits on global priority pointer 4. 27 1 qpcr_ena3 enable pcr limits on global priority pointer 3. 26 1 qpcr_ena2 enable pcr limits on global priority pointer 2. 25 1 qpcr_ena1 enable pcr limits on global priority pointer 1. 24 1 qpcr_ena0 enable pcr limits on global priority pointer 0. 23 1 reserved program and read as 0. 22 1 tun_ena7 enable tunnel on global priority pointer 7. 21 1 gfc7 enable gfc on priority pointer 7. 20 1 reserved program and read as 0. 19 1 tun_ena6 enable tunnel on global priority pointer 6. 18 1 gfc6 enable gfc on priority pointer 6. 17 1 reserved program and read as 0. 16 1 tun_ena5 enable tunnel on global priority pointer 5. 15 1 gfc5 enable gfc on priority pointer 5. 14 1 reserved program and read as 0. 13 1 tun_ena4 enable tunnel on global priority pointer 4. 12 1 gfc4 enable gfc on priority pointer 4. 11 1 reserved program and read as 0. 10 1 tun_ena3 enable tunnel on global priority pointer 3. 9 1 gfc3 enable gfc on priority pointer 3. 8 1 reserved program and read as 0. 7 1 tun_ena2 enable tunnel on global priority pointer 2. 6 1 gfc2 enable gfc on priority pointer 2. 5 1 reserved program and read as 0. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.4 scheduler registers 28236-DSH-001-B mindspeed technologies ? 14-13 0xa4 ? schedule priority control register 2 (sch_pri_2) the sch_pri_2 register sets the enables for gfc, cbr tunneling, and pcr limits on global priority queues 8 through 15. 4 1 tun_ena1 enable tunnel on global priority pointer 1. 3 1 gfc1 enable gfc on priority pointer 1. 2 1 reserved program and read as 0. 1 1 tun_ena0 enable tunnel on global priority pointer 0. 0 1 gfc0 enable gfc on priority pointer 0. bit field size name description bit field size name description 31 1 qpcr_ena_15 enable pcr limits on global priority pointer 15. 30 1 qpcr_ena_14 enable pcr limits on global priority pointer 14. 29 1 qpcr_ena_13 enable pcr limits on global priority pointer 13. 28 1 qpcr_ena_12 enable pcr limits on global priority pointer 12. 27 1 qpcr_ena_11 enable pcr limits on global priority pointer 11. 26 1 qpcr_ena_10 enable pcr limits on global priority pointer 10. 25 1 qpcr_ena_9 enable pcr limits on global priority pointer 9. 24 1 qpcr_ena_8 enable pcr limits on global priority pointer 8. 23 1 reserved program and read as 0. 22 1 tun_ena_15 enable tunnel on global priority pointer 15. 21 1 gfc15 enable gfc on global priority pointer 15. 20 1 reserved program and read as 0. 19 1 tun_ena_14 enable tunnel on global priority pointer 14. 18 1 gfc14 enable gfc on global priority pointer 14. 17 1 reserved program and read as 0. 16 1 tun_ena_13 enable tunnel on global priority pointer 13. 15 1 gfc13 enable gfc on global priority pointer 13. 14 1 reserved program and read as 0. 13 1 tun_ena_12 enable tunnel on global priority pointer 12. 12 1 gfc12 enable gfc on global priority pointer 12. 11 1 reserved program and read as 0. 10 1 tun_ena_11 enable tunnel on global priority pointer 11. 9 1 gfc11 enable gfc on global priority pointer 11. 14.0 cn8236 registers cn8236 14.4 scheduler registers atm servicesar plus with xbr traffic management 14-14 mindspeed technologies ? 28236-DSH-001-B 0xa8 ? schedule size register (sch_size) the sch_size register sets the size of the schedule table in schedule slots and the period of a schedule slot in system clocks. 8 1 reserved program and read as 0. 7 1 tun_ena_10 enable tunnel on global priority pointer 10. 6 1 gfc10 enable gfc on global priority pointer 10. 5 1 reserved program and read as 0. 4 1 tun_ena_9 enable tunnel on global priority pointer 9. 3 1 gfc9 enable gfc on global priority pointer 9. 2 1 reserved program and read as 0. 1 1 tun_ena_8 enable tunnel on global priority pointer 8. 0 1 gfc8 enable gfc on global priority pointer 8. bit field size name description bit field size name description 31 ? 16 16 tbl_size[15:0] size of schedule table in schedule slots. 15 ? 14 2 reserved program and read as 0. 13 ? 0 14 slot_per[13:0] number of system clocks per schedule slot. the value written to the register should be (slot_per ? 1). minimum bound for slot_per break value = 70. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.4 scheduler registers 28236-DSH-001-B mindspeed technologies ? 14-15 0xac ? scheduler control register (sch_ctrl) the sch_ctrl register defines the configured schedule slot and priority and vbr offsets when 16 priority queues are used. 0xb0 ? maximum abr vcc_index register (sch_abr_max) this register sets the maximum number of abr vccs being used and specifies the max_behind value. the max_behind value specifies the number of slots in the schedule table; the schedule table entry pointer can fall behind. max_behind should be set to 0 for all applications, except special multi-phy dsl applications. bit field size name description 31 ? 27 5 reserved program and read as 0. 26 1 use_schref if logic high, the schref input is used as the clock for defining a schedule table slot period in conjunction with slot_per. if logic low, sysclk is used. note: must be set to 0 during initialization unless using an external scheduler clock. 25 1 external_sch if logic high, scheduling priority is granted to externally scheduled traffic. see chapter 13.0 . 24 1 ncr_en_dest global enable for destination acr notification. 23 1 ncr_en_src global enable for source acr notification. 22 ? 18 5 ncr_stat_id identifies the status queue to be used for both source and destination acr/er notification when en_ncr_stat is asserted. 17 1 en_ncr_stat enable global status queue for both source and destination acr/er notification. 16 ? 15 2 reserved program and read as 0. 14 ? 12 3 slot_depth depth of the schedule slot is set to 1 + slot_depth words. active only if use_sch_ctrl is asserted. 11 ? 10 2 reserved program and read as 0. 9 ? 6 4 tun_pri0_offset offset from the tun_pri_0 field in the schedule table and cbr vcc table. active only if use_sch_ctrl is asserted. 5 ? 4 2 reserved program and read as 0. 3 ? 0 4 vbr_offset offset from schedule slot priority to general priority. active only if use_sch_ctrl is asserted. bit field size name description 31 ? 24 8 reserved set to 0. 14.0 cn8236 registers cn8236 14.4 scheduler registers atm servicesar plus with xbr traffic management 14-16 mindspeed technologies ? 28236-DSH-001-B 23 ? 16 8 max_behind number of slots scheduler can fall behind. for normal operations, this value should be 0. (a value of 0 results in the default value of 255 internally used.) for multi-phy dsl operations, this value should be set to the number of port used e.g., if 8 ports are used, this max_behind should be set to 16. 15 ? 0 16 vcc_max maximum abr vcc index. bit field size name description cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.4 scheduler registers 28236-DSH-001-B mindspeed technologies ? 14-17 0xb4 ? schedule abr constant register (sch_abr_con) the sch_abr_con register sets the abr trm and adtf time-out. time-out values are in units of 64 cell slots. access types: r/w 0xb8 ? abr decision table lookup base register (sch_abrbase) the sch_abrbase register sets the base address in sar-shared memory for the abr decision table. this address is 128-byte aligned, and only the 16 most significant bits of the address are specified in the sch_abrbase register. access types: r/w 0xbc ? abr congestion register (sch_cng) the sch_cng register sets each reassembly free buffer queue to a congested or non-congested state for transmitted reverse rm cells. access types: r/w bit field size name description 31 ? 16 16 abr_trm abr trm parameter. parameter value is sysclk period slot_per abr_trm 64. 15 ? 0 16 abr_adtf abr adtf parameter. parameter values is sysclk period sot_per abr_adtf 64. bit field size name description 31 ? 29 3 reserved program and read as 0. 28 1 oor_en enable abr out-of-rate forward rm cell generation. 27 ? 16 12 oor_int abr out-of-rate forward rm cell interval. a vcc is examined for an out-of-rate cell every oor_int schedule slots. 15 ? 0 16 sch_abrb[15:0] base address for the abr decision table. bit field size name description 31 ? 0 32 fbq_cng[31:0] congestion state for each free buffer queue. 14.0 cn8236 registers cn8236 14.4 scheduler registers atm servicesar plus with xbr traffic management 14-18 mindspeed technologies ? 28236-DSH-001-B 0xc0 ? pcr queue interval 0 and 1 register (pcr_que_int01) the pcr_que_int01 register fields are used to store the two lower pcr values used in pcr shaping on priority queues that have been enabled for pcr shaping by setting the qpcr_enax bits in the sch_pri register. qpcr_intx values are used in order: 3, 2, 1, and 0; highest to lowest. pcr is determined by 1 / (qpcr_intx sysclk_period slot_per). 14.4.1 0xc4 ? pcr queue interval 2 and 3 register (pcr_que_int23) the pcr_que_int23 register fields are used to store the two highest pcr values used in pcr shaping on priority queues that have been enabled for pcr shaping by setting the qpcr_enax bits in the sch_pri register. qpcr_intx values are used in order: 3, 2, 1, and 0; highest to lowest. pcr is determined by 1 / (qpcr_i24). bit field size name description 31 ? 16 16 qpcr_int1 the assigned pcr interval, entered as number of schedule table slots, used to map to the 3rd-highest priority queue that is enabled for pcr shaping (using the qpcr_enax bits in the sch_pri register). 15 ? 0 16 qpcr_int0 the assigned pcr interval, entered as number of schedule table slots, used to map to the 4th-highest priority queue that is enabled for pcr shaping (using the qpcr_enax bits in the sch_pri register). bit field size name description 31 ? 16 16 qpcr_int3 the assigned pcr interval, entered as number of schedule table slots, used to map to the highest priority queue that is enabled for pcr shaping (using the qpcr_enax bits in the sch_pri register). 15 ? 0 16 qpcr_int2 the assigned pcr interval, entered as number of schedule table slots, used to map to the 2nd-highest priority queue that is enabled for pcr shaping (using the qpcr_enax bits in the sch_pri register). cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.5 reassembly registers 28236-DSH-001-B mindspeed technologies ? 14-19 14.5 reassembly registers 0xf0 ? reassembly control register 0 (rsm_ctrl0) the reassembly control register 0 contains the general control bits for the reassembly coprocessor. the assertion of the hrst* system reset pin or the global_reset bit in the config0 register clears the rsm_enable control bit. bit field size name description 31 1 rsm_enable reassembly enable. initiates an incoming transfer if set, and halts it if reset. if this bit is reset while the reassembly coprocessor is running, it temporarily suspends the activities of the reassembly coprocessor logic. suspension takes place on a cell boundary, that is, between the completion of all processing and transfers required for the current cell, and the start of processing for the next cell. the hold can be removed and the transfer resumed by setting the rsm_enable bit. this bit is also set low internally on certain reassembly error conditions. this includes parity error with phalt_en. in this case, the error condition should be corrected and the rsm_enable bit set high to resume operation. 30 1 rsm_reset reassembly reset. forces a hardware reset of the reassembly coprocessor when asserted. it must be deasserted before the reassembly coprocessor resumes normal operation. 29 1 reserved program and read as 0. 28 1 vpi_mask vpi mask enable. used to select uni/nni header operation in the direct index method. when a logic high, the four msbs of the header are masked for uni operation. this also controls the index table size. a uni table is 256 entries and a nni table is 4096. 27 ? 24 4 reserved program and read as 0. 23 ? 18 6 reserved program and read as 0. 17 1 rsm_phalt reassembly coprocessor halt on parity error detect. the reassembly coprocessor halts the incoming channel logic if a parity error is detected and the rsm_phalt bit is set. 16 1 prepend_index causes vcc_index to be prepended to the bom cell transfer. 15 1 fwall_en firewall enable. enables free buffer queue firewalling of user cells. if set, this bit enables the per connection free buffer queue firewall. each connection that firewall is active in must have the fw_en bit set to a logic high in the vcc table. 14 1 rsm_fbq_dis free buffer queue underflow protection disable. when a logic high, the reassembly coprocessor ignores the vld bit in the free buffer queue when a new buffer is required. the periodic writing of the read index pointer to host/sar-shared memory is also disabled. 13 1 rsm_stat_dis status queue overflow protection disable. when a logic high, the reassembly coprocessor ignores the read_ud pointer. 14.0 cn8236 registers cn8236 14.5 reassembly registers atm servicesar plus with xbr traffic management 14-20 mindspeed technologies ? 28236-DSH-001-B 12 1 gto_en global time-out enable. when a logic high, the automatic reassembly time-out function is enabled. 11 ? 5 7 max_len maximum length. max_len 1024 is the maximum allowable size in bytes of an aal5 cpcs-pdu, including overhead. 4 ? 0 5 gdis_pri global discard priority. used by the frame relay and clp discard functions. if the individual channel priority number is less than or equal to gdis_pri, pdus on that channel can be discarded. bit field size name description cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.5 reassembly registers 28236-DSH-001-B mindspeed technologies ? 14-21 0xf4 ? reassembly control register 1 (rsm_ctrl1) the reassembly control register 1 contains additional general control bits for the reassembly coprocessor. bit field size name description 31 1 en_prog_blk_sz enable programmable block size. when a logic high, the programmable block size vpi/vci lookup method is enabled. this method consists of programmable block sizes, and an additional blk_en bit in the vci index table. 30 ? 28 3 vci_it_blk_sz vcc table/vci index table block size. this field determines the number of rsm vcc entries accessed per vci index table entry. 27 1 en_vpi_size if logic high, enables an expanded, more flexible vpi index table configuration. the vpi_size register and port_id from the framer are used to calculate an index into the vpi index table. 26 ? 24 3 reserved program and read as 0. 23 ? 20 4 reserved program and read as 0. 19 ? 17 3 reserved program and read as 0. 16 ? 13 4 reserved program and read as 0. 12 1 oam_ff_dsc oam fifo buffer full discard. when a logic high and oam_qu_en is a logic high, an oam cell is discarded if the incoming dma fifo buffer is almost full. 11 1 oam_en oam enable. enables detection and processing of oam cells. 10 1 oam_qu_en oam buffer/status queue enable. when a logic high, an oam cell uses the global oam free buffer queue and status queue instead of per-channel resources. 9 ? 5 5 oam_bfr_qu oam free buffer queue. when oam_qu_en is a logic high, oam cells uses, buffers from the free buffer queue identified by oam_bfr_qu. 4 ? 0 5 oam_stat_qu oam status queue. when oam_qu_en is a logic high, oam cells posts status to the status queue identified by oam_stat_qu. value vcc block_size 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 not valid. 14.0 cn8236 registers cn8236 14.5 reassembly registers atm servicesar plus with xbr traffic management 14-22 mindspeed technologies ? 28236-DSH-001-B 0xf8 ? reassembly free buffer queue base register (rsm_fqbase) this register determines the base address of both banks of contiguous free buffer queue spaces. the base address is a 16-bit number. since both banks reside in sar-shared memory (23-bits of byte addressing), the structures can start on 128 byte boundaries. bank 0 has additional boundary requirements if the buffer return mechanism is enabled. 0xfc ? reassembly free buffer queue control register (rsm_fqctrl) this register contains free buffer queue control information. bit field size name description 31 ? 16 16 fbq1_base free buffer queue bank 1 base address. 15 ? 0 16 fbq0_base free buffer queue bank 0 base address. bit field size name description 31 ? 16 16 reserved not implemented at this time. 15 ? 14 2 fbq_size free buffer queue size. selects the size of all free buffer queues. 0 = 64 1 = 256 2 = 1,024 3 = 4,096 13 1 fwd_rnd buffer return processing priority selection. when a logic low, buffer return entries are processed from queues in priority fashion with queue 15 having the highest priority. when a logic high, round-robin arbitration is used. 12 1 fbq0_rtn free buffer queue 0 buffer return enable. when a logic high, bank 0 is enabled to process buffer return for firewall operation. when this bit is set, queue entries 0 ? 15 are four words independent of the value of fwd_en; otherwise, they are two words. 11 ? 8 4 fwd_en forward processing enable. selects the number of free buffer queues in bank 0 that have buffer return processing enabled. starting with free buffer queue 0, a value of 0 in fwd_en selects only one queue, and a value of 15 selects 16 queues. 7 ? 0 8 fbq_ud_int free buffer queue update interval. this value determines how many buffers are taken off the free buffer queue before the reassembly coprocessor writes the current read index pointer to host or sar-shared memory. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.5 reassembly registers 28236-DSH-001-B mindspeed technologies ? 14-23 0x100 ? reassembly table base register (rsm_tbase) this register consists of a 16-bit address pointer that points to the beginning of the vpi index table, and a 16-bit address pointer that points to the beginning of the rsm vcc table. since both tables reside in sar-shared memory, the tables start on 128-byte boundaries. the size of the vpi index table used in the direct index method is dependent upon the setting of rsm_ctrl0(vpi_mask). 0x104 ? reassembly time-out register (rsm_to) 0x108 ? reassembly/segmentation queue base address register (rs_qbase) this register contains the 128-byte aligned base address of the reassembly/segmentation queue structure. bit field size name description 31 ? 16 16 rsm_vccb reassembly vcc table base address. 15 ? 0 16 rsm_itb vpi index table base address. bit field size name description 31 ? 16 16 rsm_to_per reassembly time-out interrupt period. the value in this register determines the number of sysclk periods for each time-out interrupt. a value of 0 divides by 65,538. 15 ? 0 16 rsm_to_cnt reassembly time-out counter. the value in this register plus one determines the number of time-out interrupts that occur in each pass through the rsm vcc table. bit field size name description 31 ? 18 14 reserved program and read as 0. 17 ? 16 2 rs_size[1:0] size of the rs queue. each rs queue entry is eight octets in length. 00 = 256 01 = 1,024 10 = 4,096 11 = 16,384 15 ? 0 16 rs_qbase[15:0] base address of the reassembly/segmentation queue. 14.0 cn8236 registers cn8236 14.5 reassembly registers atm servicesar plus with xbr traffic management 14-24 mindspeed technologies ? 28236-DSH-001-B 0x10c ? reassembly er_shift tables base register (ers_base) this register sets the base address in src local memory for the er_shift tables used in implicit host congestion er reduction. the base addresses are 128-byte aligned, and only the 16 most significant bits of the address are specified in the ers_base register. 0x110 ? variable vpi size register (vpi_size) this register determines the maximum vpi allowed per port. bit field size name description 31 ? 16 16 reserved program and read as 0. 15 ? 0 16 er_shift_b[15:0] base address for the er_shift tables. bit field size name description 31 ? 28 4 max_vpi7 maximum vpi for port. value max vpi value 0off 11 23 37 415 531 663 7127 8255 9511 a1,023 b2,047 c4,095 d not used e not used f not used 27 ? 24 4 max_vpi6 maximum vpi for port 6. 23 ? 20 4 max_vpi5 maximum vpi for port 5. 19 ? 16 4 max_vpi4 maximum vpi for port 4. 15 ? 12 4 max_vpi3 maximum vpi for port 3. 11 ? 8 4 max_vpi2 maximum vpi for port 2. 7 ? 4 4 max_vpi1 maximum vpi for port 1. 3 ? 0 4 max_vpi0 maximum vpi for port 0. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.5 reassembly registers 28236-DSH-001-B mindspeed technologies ? 14-25 0x114 ? transmit port register (tx_fifo_ctrl) this register sets a counter compare value that is used for the head of line flushing mechanism of the transmit fifo. if head of line flushing is enabled in configuration register 1, a counter is reset when the utopia master in multi-phy mode puts out the address of a phy device, and the counter is increased based on utopia tx_clk. once the counter reaches the tx_cntr value and no utopia clav signal have been received from the phy device, the cell in the fifo is discarded. tx_cntr must not have a value of 0 if the head of line flushing mechanism is enabled. 0x118 ? transmit port control register this register disables utopia ports if the tx_fifo_flush_en bit in configuration register 1 is set. if bit x of the tx_port_dis bitmap is set, cells belonging to phy x are being discarded. no tx_status bit are set. bit field size name description 31 ? 16 16 reserved set to 0. 15 ? 0 16 tx_cntr counter values to tx fifo flush mechanism. bit field size name description 31 ? 8 24 reserved set to 0. 7 ? 0 8 tx_port_dis[7:0] disables phy port x. 14.0 cn8236 registers cn8236 14.6 counters and status registers atm servicesar plus with xbr traffic management 14-26 mindspeed technologies ? 28236-DSH-001-B 14.6 counters and status registers 0x160 ? atm cells transmitted counter (cell_xmit_cnt) this register counts the number of user data cells transmitted by the segmentation coprocessor. the counter is reset to 0 by an assertion of either the hrst* system reset pin or the global_reset bit in the config0 register. optionally, an interrupt can be programmed when the counter rolls over. 0x164 ? atm cells received counter (cell_rcvd_cnt) this register counts the number of assigned cells received by the reassembly coprocessor. the counter is reset to 0 by an assertion of either the hrst* system reset pin or the global_reset bit in the config0 register. optionally, an interrupt can be programmed when the counter rolls over. 0x168 ? atm cells discarded counter (cell_dsc_cnt) this register counts the number of unassigned cells received by the reassembly coprocessor. the counter is reset to 0 by an assertion of either the hrst* system reset pin or the global_reset bit in the config0 register. optionally, an interrupt can be programmed when the counter rolls over. bit field size name description 31 ? 0 32 cell_xmit_cnt count of user data cells transmitted. bit field size name description 31 ? 0 32 cell_rcvd_cnt count of assigned received cells. bit field size name description 31 ? 0 32 cell_dsc_cnt count of unassigned cells dropped. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.6 counters and status registers 28236-DSH-001-B mindspeed technologies ? 14-27 0x16c ? aal5 pdus discarded counter (aal5_dsc_cnt) this register counts the number of aal5 cpcs-pdus discarded due to buffer firewall, buffer underflow, or status overflow. the counter is reset to 0 by an assertion of either the hrst* system reset pin or the global_reset bit in the config0 register. optionally, an interrupt can be programmed when the counter rolls over. 0x1a0 ? host mailbox register (host_mbox) this register implements a mailbox for communication between the host and local processors. the register is written by the local processor and read by the host to pass messages in that direction. writes to this register can interrupt the host, while reads can interrupt the local processor. 0x1a4 ? host status write register (host_st_wr) this register indicates if a reassembly or segmentation host-located status queue has been written. only queues 0 through 15 are supported. all bits are latched until read by the host. the rsm_hs_write[15:0] bits are ored together into host/lp_istat0(rsm_hs_write), and the seg_hw_write[15:0] bits are ored together into host/lp_istat0(seg_hs_write). bit field size name description 31 ? 16 16 reserved not implemented at this time. 15 ? 0 16 aal5_dsc_cnt aal5 pdus discarded by the reassembly coprocessor. bit field size name description 31 ? 0 32 host_mbox[31:0] messages flow from local processor to host. bit field size name description 31 ? 16 16 rsm_hs_write[15:0] indication that a host-located reassembly status queue entry has been written. only queues 0 through 15 are supported. 15 ? 0 16 seg_hs_write[15:0] indication that a host-located segmentation status queue entry has been written. only queues 0 through 15 are supported. 14.0 cn8236 registers cn8236 14.6 counters and status registers atm servicesar plus with xbr traffic management 14-28 mindspeed technologies ? 28236-DSH-001-B 0x1a8 ? aalx_stat register (aalx_stat) this register provides the status of the aalx shadow counters. all bits are latched until read. any bit set to a logic high causes the aalx_stat bit to be set in the host_istat1 and lp_istat1 registers. 0x1ac ? transmit port cell discard status register (tx_status) this register indicates the status of a phy device. if the head of line flushing mechanism is enabled (tx_fifo_flush_en set in configuration register 1), this register indicates if a cell has been discarded due to the head of line flushing mechanism. if a bit x of the tx_stat bitmap is set, phy x discarded a cell. if 1 or more bits of tx_stat is set, an interrupt is generated (if enabled). the tx_stat bitmap is latched until the tx_status register is read by the host. 0x1b0 ? local processor mailbox register (lp_mbox) this register implements a mailbox for communication between the host and local processors. lp_mbox is written by the host processor and read by the local processor to pass messages in that direction. writes to this register can interrupt the local processor while reads can interrupt the host processor. bit field size name description 31 ? 22 10 reserved always read as 0. 21 ? 16 6 aalx_rsm_ovfl[5:0] a cell was discarded since the ingress fifo buffer of port x was full. 15 ? 14 2 reserved always read as 0. 13 ? 8 6 aalx_rsm_unfl[5:0] a hfifordx edge was detected when the ingress fifo buffer shadow counter was empty. 7 ? 6 2 reserved always read as 0. 5 ? 0 6 aalx_seg_ovfl[5:0] a hfifowrx edge was detected when the egress fifo buffer shadow counter was full. bit field size name description 31 ? 8 24 reserved set to 0. 7 ? 0 8 tx_stat[7:0] status of tx port x. bit field size name description 31 ? 0 32 lp_mbox[31:0] local processor mailbox register. messages flow from host processor to local processor. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.6 counters and status registers 28236-DSH-001-B mindspeed technologies ? 14-29 14.6.1 host interrupt status registers these two registers contain all interruptible status bits for the host processor. the corresponding interrupt enables are located in the host_imaskx registers. status types are defined as follows: l level-sensitive status ? a logic 1 on the status bit causes an interrupt when enabled by the corresponding imask bit. reading the status does not clear the status or interrupt. the source of the condition causing the status must be cleared before the status or interrupt is cleared. e event driven status ? a 0 > 1 transition on the status bit causes an interrupt when enabled. reading the status register clears the status bit and the interrupt. de dual event status ? a 0 > 1 and 1 > 0 transition on the status bit can be enabled to cause an interrupt. reading the status register clears the status bit and the interrupt. note: only host reads reset the status bits in the host_istat0 register. 14.0 cn8236 registers cn8236 14.6 counters and status registers atm servicesar plus with xbr traffic management 14-30 mindspeed technologies ? 28236-DSH-001-B table 14-3. 0x1c0 ? host processor interrupt status register 0 (host_istat0) bit field size type name description 31 1 l pfail reflects inverted state of processor pfail* input. 30 1 l phy_intr in standalone operation, this bit reflects the inverted state of the pdaen* input. phy_intr can be connected to a phy interrupt source. 29 1 ? reserved read as 0. 28 1 e host_mbox_ written this bit is set upon a write to the host_mbox register by the local processor, and cleared by a read of the host_mbox register. 27 1 e lp_mbox_read this bit is set upon the read of the lp_mbox register by the local processor. 26 1 ? reserved read as 0. 25 ? 24 2 ? reserved read as 0. 23 1 ? reserved read as 0. reserved for future status page expansion. 22 1 l hstat1 this bit is set when any bit in host_istat1 is set. 21 ? 19 3 ? reserved read as 0. 18 1 e gfc_link set when three consecutive received cells have gfc set_a, set_b, or halt bits set. 17 1 l rsm_run set when the reassembly machine is running. is high when the rsm coprocessor is processing a cell. 16 1 l rsm_hs_write indicates reassembly host status has been written by cn8236 to status queues 0 through 15. for queue number, read host_st_wr, which must be read in order to clear status bit. 15 1 e rsm_ls_write indicates reassembly local status has been written by cn8236. 14 ? 12 3 ? reserved read as 0. 11 1 l seg_run set when the segmentation machine is running. is high when seg_enable bit in seg_ctrl is high or when processing the last cell after seg_enable is low. 10 1 l seg_hs_write indicates segmentation host status has been written by the cn8236 to status queues 0 through 15. for queue number, read host_st_wr which must be read in order to clear status bit. 9 1 e seg_ls_write indicates that a segmentation local status queue has been written by the cn8236. 8 ? 45 ? reserved read as 0. 3 1 e aal5_dsc_rlovr set on the occurrence of an aal5_dsc_cnt rollover. 2 1 e cell_dsc_rlovr set on the occurrence of a cell_dsc_cnt rollover. 1 1 e cell_rcvd_rlovr set on the occurrence of a cell_rcvd_cnt rollover. 0 1 e cell_xmt_rlovr set on the occurrence of a cell_xmit_cnt rollover. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.6 counters and status registers 28236-DSH-001-B mindspeed technologies ? 14-31 table 14-4. 0x1c4 ? host processor interrupt status register 1 (host_istat1) bit field size type name description 31 1 l pci_bus_eror this bit is set if the merror bit in the pci configuration register is set. the merror bit is reset by either writing a logic 1 to the merror bit in the pci configuration register, or setting the config0(pci_err_reset) bit to a logic high. 30 1 l aalx_stat whenever any bit in aalx_stat is a logic 1, aalx_stat is a logic 1. 29 1 l tx_discard when any bit in tx_status is a logic 1, tx_discard is a logic 1. tx_discard is reset to 0 after the host reads the tx_status register. 28 ? 27 2 ? reserved read as 0. 26 1 e dma_afull set when the incoming dma burst fifo buffer becomes almost full. 25 1 e fr_par_err set on the occurrence of a parity error on the reassembly atm physical interface. 24 1 e fr_sync_err set on the occurrence of a synchronization error on the reassembly atm physical interface. 23 ? 16 8 ? reserved read as 0. 15 1 e rs_queue_full reassembly/segmentation queue full condition. 14 1 e rsm_ovfl reassembly overflow. indicates that a cell was lost due to a fifo buffer full condition. 13 1 e rsm_hs_full set on the occurrence of a host status queue full condition. 12 1 e rsm_ls_full set on the occurrence of a local status queue full condition. 11 1 e rsm_hf_empt set on the occurrence of a host free buffer queue empty condition. 10 1 e rsm_lf_empt set on the occurrence of a local free buffer queue empty condition. 9 ? 37 ? reserved read as 0. 2 1 e seg_unfl segmentation underflow indicates that a scheduled cell could not be sent due to lack of pci bandwidth. 1 1 e seg_hs_full indicates that the segmentation host status queue is full. 0 1 e seg_ls_full indicates that the segmentation local status queue is full. 14.0 cn8236 registers cn8236 14.6 counters and status registers atm servicesar plus with xbr traffic management 14-32 mindspeed technologies ? 28236-DSH-001-B this register contains the interrupt enables that correspond to the status bits in the host_istat0 register. the assertion of the hrst* system reset pin clears all of the host_imask0 interrupt enables. table 14-5. 0x1d0 ? host interrupt mask register 0 (host_imask0) bit field size name description 31 1 en_pfail enables interrupt when pfail status is a logic 1. 30 1 en_phy_intr enables interrupt when phy_intr status is a logic 1. 29 1 reserved set to 0. 28 1 en_host_mbox_written enables interrupt when host_mbox written status is a logic 1. 27 1 en_lp_mbox_read enables interrupt when lp_mbox_read status is a logic 1. 26 1 reserved set to 0. 25 ? 24 2 reserved set to 0. 23 1 reserved set to 0. reserved for future status page expansion. 22 1 en_hstat1 global interrupt enable for host_istat1 status register. individual interrupts in host_istat1 are enabled in host_imask1. 21 ? 19 3 reserved set to 0. 18 1 en_gfc_link enables interrupt when gfc_link status is a logic 1. 17 1 en_rsm_run enables interrupt when rsm_run status is a logic 1. 16 1 en_rsm_hs_write enables interrupt when rsm_hs_write status is a logic high. 15 1 en_rsm_ls_write enables interrupt when rsm_ls_write status is a logic high. 14 ? 12 3 reserved set to 0. 11 1 en_seg_run enables interrupt when seg_run status is a logic high. 10 1 en_seg_hs_write enables interrupt when seg_hs_write status is a logic high. 9 1 en_seg_ls_write enables interrupt when seg_ls_write status is a logic high. 8 ? 4 5 reserved set to 0. 3 1 en_aal5_dsc_rlovr enables an interrupt when aal5_dsc_rlovr status is a logic high. 2 1 en_cell_dsc_rlovr enables an interrupt when cell_dsc_rlovr status is a logic high. 1 1 en_cell_rcvd_rlovr enables an interrupt when cell_rcvd_rlovr status is a logic high. 0 1 en_cell_xmit_rlovr enables an interrupt when cell_xmit_rlovr status is a logic high. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.6 counters and status registers 28236-DSH-001-B mindspeed technologies ? 14-33 this register contains the interrupt enables that correspond to the status in the host_istat1 register. the assertion of the hrst* system reset pin clears all of the host_imask1 interrupt enables. table 14-6. 0x1d4 ? host interrupt mask register 1 (host_imask1) bit field size name description 31 1 en_pci_bus_error enables interrupt when pci_bus_error status is a logic 1. 30 1 en_aalx_stat enables interrupt when host_istat1 (aalx_stat) is a logic 1. 29 1 en_tx_discard enables interrupt when host_istat1 (tx_discard) is a logic 1. 28 ? 27 2 reserved set to 0. 26 1 en_dma_afull enabled interrupt when dma_afull status is a logic 1. 25 1 en_fr_par_err enables interrupt when fr_par_err status is a logic 1. 24 1 en_fr_sync_err enables interrupt when fr_sync_err status is a logic 1. 23 ? 16 8 reserved set to 0. 15 1 en_rsqueue_full enables interrupt when rsqueue_full status is a logic 1. 14 1 en_rsm_ovfl enables interrupt when rsm_ovfl status is a logic 1. 13 1 en_rsm_hs_full enables interrupt when rsm_hs_full status is a logic high. 12 1 en_rsm_ls_full enables interrupt when rsm_ls_full status is a logic high. 11 1 en_rsm_hf_empt enables interrupt when rsm_hf_empt status is a logic high. 10 1 en_rsm_lf_empt enables interrupt when rsm_lf_empt status is a logic high. 9 ? 3 7 reserved set to 0. 2 1 en_seg_unfl enables interrupt when seg_unfl status is a logic high. 1 1 en_seg_hs_full enables interrupt when seg_hs_full status is a logic high. 0 1 en_seg_ls_full enables interrupt when seg_ls_full status is a logic high. 14.0 cn8236 registers cn8236 14.6 counters and status registers atm servicesar plus with xbr traffic management 14-34 mindspeed technologies ? 28236-DSH-001-B 14.6.2 local processor interrupt status registers the local processor interrupt status registers contain all the interruptible status bits for the local processor. the corresponding interrupt enables are located in the lp_imaskx registers. status types are defined as follows: l level sensitive status ? a logic 1 on the status bit causes an interrupt when enabled by the corresponding imask bit. reading the status does not clear the status or interrupt. the source of the condition causing the status must be cleared before the status or interrupt is cleared. e event driven status ? a 0 > 1 transition on the status bit causes an interrupt when enabled. reading the status register clears the status bit and the interrupt. de dual event status ? a 0 > 1 and 1 > 0 transition on the status bit can be enabled to cause an interrupt. reading the status register clears the status bit and the interrupt. note: only local processor reads reset the status bits in the lp_istat0 register. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.6 counters and status registers 28236-DSH-001-B mindspeed technologies ? 14-35 table 14-7. 0x1e0 ? local processor interrupt status register 0 (lp_istat0) bit field size type name description 31 1 e rtc_ovfl clock register overflow. 30 1 e alarm1 set when alarm1 register matches clock register. 29 1 ? reserved read as 0. 28 1 e lp_mbox_written this bit is set upon a write to the lp_mbox register by the host processor. 27 1 e host_mbox_read this bit is set upon the read of the host_mbox register by the host processor. 26 1 ? reserved read as 0. 25 ? 24 2 ? reserved read as 0. 23 1 ? reserved read as 0. reserved for future status page expansion. 22 1 l lstat1 this bit is set when any bit in lp_istat1 is set. 21 ? 19 3 ? reserved read as 0. 18 1 e gfc_link set when three consecutive received cells have gcf set_a, set_b, or halt bits set. 17 1 l rsm_run set when the reassembly machine is running. is high when the rsm coprocessor is processing a cell. 16 1 l rsm_hs_write indicates reassembly host status has been written by the cn8236 to status queues 0 through 15. for queue number, read host_st_wr which must be read in order to clear status bit. 15 1 e rsm_ls_write indicates that a reassembly local status queue has been written by the cn8236. 14 ? 12 3 ? reserved read as 0. 11 1 l seg_run set when the segmentation machine is running. is high when seg_enable bit in seg_ctrl is high or when processing the last cell after seg_enable is set low. 10 1 l seg_hs_write indicates segmentation host status has been written by the cn8236 to status queues 0 through 15. for queue number, read host_st_wr, which must be read in order to clear status bit. 9 1 e seg_ls_write indicates that a segmentation local status queue has been written by the cn8236. 8 ? 45 ? reserved read as 0. 3 1 e aal5_dsc_rlovr set on the occurrence of an aal5_dsc_cnt rollover. 2 1 e cell_dsc_rlovr set on the occurrence of a cell_dsc_cnt rollover. 1 1 e cell_rcvd_rlovr set on the occurrence of a cell_rcvd_cnt rollover. 0 1 e cell_xmit_rlovr set on the occurrence of a cell_xmit_cnt rollover. 14.0 cn8236 registers cn8236 14.6 counters and status registers atm servicesar plus with xbr traffic management 14-36 mindspeed technologies ? 28236-DSH-001-B table 14-8. 0x1e4 ? local processor interrupt status register 1 (lp_istat1) bit field size type name description 31 1 l pci_bus_eror this bit is set if the merror bit in the pci configuration register is set. the merror bit is reset by either writing a logic 1 to the merror bit in the pci configuration register, or setting the config0(pci_err_reset) bit to a logic high. 30 1 l aalx_stat whenever any bit in aalx_stat is a logic 1, aalx_stat is a logic 1. 29 1 l tx_discard when any bit in tx_status is a logic 1, tx_discard is reset to 0 after the host reads the tx_status register. 28 ? 27 2 ? reserved read as 0. 26 1 e dma_afull set when the incoming dma burst fifo buffer becomes almost full. 25 1 e fr_par_err set on the occurrence of a parity error on the reassembly atm physical interface. 24 1 e fr_sync_err set on the occurrence of a synchronization error on the reassembly atm physical interface. 23 ? 16 8 ? reserved read as 0. 15 1 e rs_queue_full reassembly/segmentation queue full condition. 14 1 e rsm_ovfl reassembly overflow. indicates that a cell was lost due to a fifo buffer full condition. 13 1 e rsm_hs_full set on the occurrence of a host status queue full condition. 12 1 e rsm_ls_full set on the occurrence of a local status queue full condition. 11 1 e rsm_hf_empt set on the occurrence of a host free buffer queue empty condition. 10 1 e rsm_lf_empt set on the occurrence of a local free buffer queue empty condition. 9 ? 37 ? reserved read as 0. 2 1 e seg_unfl segmentation underflow indicates that a scheduled cell could not be sent due to lack of pci bandwidth. 1 1 e seg_hs_full indicates that the segmentation host status queue is full. 0 1 e seg_ls_full indicates that the segmentation local status queue is full. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.6 counters and status registers 28236-DSH-001-B mindspeed technologies ? 14-37 this register contains the interrupt enables that correspond to the status in the lp_istat0 register. the assertion of the hrst* system reset pin clears all of the lp_imask0 interrupt enables. table 14-9. 0x1f0 ? local processor interrupt mask register 0 (lp_imask0) bit field size name description 31 1 en_rtc_ovfl enables an interrupt when rtc_ovfl status is a logic high. 30 1 en_alarm1 enables an interrupt when alarm1 status is a logic 1. 29 1 reserved set to 0. 28 1 en_lp_mbox_written enables an interrupt when lp_mbox_written status is a logic 1. 27 1 en_host_mbox_read enables an interrupt when host_mbox_read status is a logic 1. 26 1 reserved set to 0. 25 ? 24 2 reserved set to 0. 23 1 reserved set to 0. reserved for future status page expansion. 22 1 en_lstat1 global interrupt enable for lp_istat1 status register. individual interrupts of lp_istat1 are enabled in lp_imask1. 21 ? 19 3 reserved set to 0. 18 1 en_gfc_link enables an interrupt when gfc_link status is a logic 1. 17 1 en_rsm_run enables an interrupt when rsm_run status is a logic 1. 16 1 en_rsm_hs_write enables an interrupt when rsm_hs_write status is a logic high. 15 1 en_rsm_ls_write enables an interrupt when rsm_ls_write status is a logic high. 14 ? 12 3 reserved set to 0. 11 1 en_seg_run enables an interrupt when seg_run status is a logic high. 10 1 en_seg_hs_write enables an interrupt when seg_hs_write status is a logic high. 9 1 en_seg_ls_write enables an interrupt when seg_ls_write status is a logic high. 8 ? 4 5 reserved set to 0. 3 1 en_aal5_dsc_rlovr enables an interrupt when aal5_dsc_rlovr status is a logic high. 2 1 en_cell_dsc_rlovr enables an interrupt when cell_dsc_rlovr status is a logic high. 1 1 en_cell_rcvd_rlovr enables an interrupt when cell_rcvd_rlovr status is a logic high. 0 1 en_cell_xmit_rlovr enables an interrupt when cell_xmit_rlovr status is a logic high. 14.0 cn8236 registers cn8236 14.6 counters and status registers atm servicesar plus with xbr traffic management 14-38 mindspeed technologies ? 28236-DSH-001-B this register contains the interrupt enables that correspond to the statuses in the lp_istat1 register. the assertion of the hrst* system reset pin clears all of the lp_imask1 interrupt enables. table 14-10. 0x1f4 ? local processor interrupt mask register 1 (lp_imask1) bit field size name description 31 1 en_pci_bus_error enables an interrupt when pci_bus_error status is a logic 1. 30 1 en_aalx_stat enables interrupt when host_istat1(aalx_stat) is a logic 1. 29 1 en_tx_discard enables an interrupt when lp_stat1(tx_discard) is a logic 1. 28 ? 27 2 reserved set to 0. 26 1 en_dma_afull enables an interrupt when dma_afull status is a logic 1. 25 1 en_fr_par_err enables an interrupt when fr_par_err status is a logic 1. 24 1 en_fr_sync_err enables an interrupt when fr_sync_err status is a logic 1. 23 ? 16 8 reserved set to 0. 15 1 en_rsqueue_full enables an interrupt when rsququq_full status is a logic 1. 14 1 en_rsm_ovfl enables an interrupt when rsm_ovfl status is a logic 1. 13 1 en_rsm_hs_full enables an interrupt when rsm_hs_full status is a logic high. 12 1 en_rsm_ls_full enables an interrupt when rsm_ls_full status is a logic high. 11 1 en_rsm_hs_empt enables an interrupt when rsm_hs_empt status is a logic high. 10 1 en_rsm_ls_empt enables an interrupt when rsm_ls_empt status is a logic high. 9 ? 3 7 reserved set to 0. 2 1 en_seg_unfl enables an interrupt when seg_unfl status is a logic high. 1 1 en_seg_hs_full enables an interrupt when seg_hs_full status is a logic high. 0 1 en_seg_ls_full enables an interrupt when seg_ls_full status is a logic high. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.7 pci bus interface registers 28236-DSH-001-B mindspeed technologies ? 14-39 14.7 pci bus interface registers in accordance with the pci bus specification, revision 2.1, the sar pci bus interface implements a 128-byte configuration register space. these configuration registers are used by the host processor to initialize, control, and monitor the pci bus interface logic. the complete definitions of these registers and the relevant fields within them are given in the pci bus specification, and are not repeated here. the implementation of the configuration space registers in the cn8236 is shown in table 14-11 . table 14-12 provides descriptions of fields and other registers within the pci configuration space. table 14-13 details the pci command register and table 14-14 shows the pci status register breakdown. the pci special status register is detailed in table 14-15 . table 14-16 details the eprom register. table 14-11. pci configuration register byte addr pci configuration register layout 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 device_id (0x8236) vendor_id (0x14f1) 0x04 status command 0x08 class_code (0x020300) rev_id (0x00) 0x0c reserved header_type (0x00) lat_timer cache_line_size (0x00) 0x10 base_address_register_0 0x14 ? 0x28 reserved 0x2c subsystem_id (sid) subsystem_vendor_id (svid) 0x30 reserved 0x34 reserved capability_ptr (0x50) 0x38 reserved 0x3c max_latency (0x05) min_grant (0x02) interrupt_pin (0x01) interrupt_line 0x40 special_status_register 0x44 master_read_addr 0x48 master_write_addr 0x4c eeprom_register 0x50 pm_capability next_cap_ptr capability_id (0x01) 0x54 pm_data reserved pmcsr 0x58 ? 0x7c reserved (0x00000000) 14.0 cn8236 registers cn8236 14.7 pci bus interface registers atm servicesar plus with xbr traffic management 14-40 mindspeed technologies ? 28236-DSH-001-B table 14-12. pci register configuration register field descriptions (1 of 2) bit description device_id 16-bit device identifier. serves to uniquely identify the sar to the host operating system. set to 0x8236. vendor_id 16-bit vendor identifier code, allocated on a global basis by the pci special interest group. set to 0x14f1. status pci bus interface status register. the pci host can monitor its operation using the status field. this field is further divided into subfields as shown below. these bits can be reset by writing a logic high to the appropriate bit. see the status register below for a description of the bits in the register. command pci bus interface control/command register. the pci host can configure the sar bus interface logic using the command field. this field is further divided into subfields as shown below. active hrst* input causes all bits to be a logic 0. see the command register below for a description of the bits in the register. class_code the class_code register is read-only and is used to identify the generic function of the device. see pci bus specification revision 2.1 for the specific allowed settings for this field. set to 0x020300 (indicates a network controller, specifically an atm controller). rev_id revision id code for the cn8236 chip: 0 = rev a and 2 = rev b. header_type this field identifies the layout of the second part of the predefined header of the pci configuration space (beginning at 0x10). see pci local bus specification , revision 2.1 for the specific possible settings for this field. set to 0x00. lat_timer latency timer. value after hrst* active is 0x00. all bits are writable. the suggested value is 0x10 in order to allow the complete transfer of a cell. cache_line_size this read/write register specifies the system cacheline size in units of 32-bit words. must be initialized to 0x00 at initialization and reset. base_address _register_0 base address of pci address space occupied by the cn8236 (as seen and assigned by the host processor). value after hrst* active is 0x00. subsystem_id (sid) this register value is used to uniquely identify the add-in board or subsystem where the pci device resides. thus, it provides a mechanism for add-in card vendors to distinguish their cards from one another even though the cards may have the same pci controller on them (and therefore the same device_id). subsystem _vendor_id (svid) this register value is used to uniquely identify the vendor of an add-in board or subsystem where the pci device resides. thus, it provides a mechanism for add-in card vendors to distinguish their cards from one another even though the cards can have the same pci controller on them (and therefore the same vendor_id). capability_ptr this field provides an offset into the pci configuration space for the location of the first item in the capabilities linked list. set to 0x50. max_latency this read-only register specifies how often the cn8236 device needs to gain access to the pci bus, assuming a clock rate of 33 mhz. set to 0x02 (a period of time in units of 1/4 s). min_grant this read-only register specifies how long of a burst period the cn8236 device needs to gain access to the pci bus. set to 0x02 (a period of time in units of 1/4 s). interrupt_pin this read-only register tells which interrupt pin the device (or device function) uses. set to 0x01 (corresponds to interrupt pin inta#). interrupt_line interrupt line identifier. the value in this register tells which input of the system interrupt controller(s) the device ? s interrupt pin is connected to. the device itself does not use this value; rather, it is used by device drivers and operating systems. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.7 pci bus interface registers 28236-DSH-001-B mindspeed technologies ? 14-41 special_status _register device status not defined by the pci specification. (the field is further subdivided into subfields as described in table 14-15 .) detailed descriptions of these subfields can be found in the pci bus specification. the configuration registers are accessed starting from byte address 0 in the configuration space allotted to an adapter card containing the sar chip. access to the configuration registers is available only to the pci host cpu, and is independent of all other sar logic. master_read _addr current read target address used by pci bus master (read only). master_write _addr current write target address used by pci bus master (read only). eeprom_register a 32-bit register controlling access to the serial eeprom. (see table 14-16 for a description of the specific fields in the eeprom_register.) pm_capability power management capabilities register. a 16-bit read-only register which provides information on the capabilities of the function related to power management. see the pci bus power management interface specification revision 1.0 for specific information related to this register. next_cap_ptr next item pointer register. this field provides an offset into the pci configuration space pointing to the location of the next item of the linked capability list. if there are no additional items in the capabilities list, this register is set to 0x00. capability_id capability identifier. when set to 0x01, indicates that the linked list item being pointed to is the pci power management registers. default value is 0x01. pm_data power management data register. this 8-bit read-only register provides a mechanism for the power management function to report state-dependent operating data, such as power consumed or heat dissipation. see the pci bus power management interface specification revision 1.0 for specific information related to this register. pmcsr power management control/status register. this 16-bit register is used to manage the pci function ? s power management state, and to enable and monitor power management events. see the pci bus power management interface specification revision 1.0 for specific information related to this register. table 14-12. pci register configuration register field descriptions (2 of 2) bit description 14.0 cn8236 registers cn8236 14.7 pci bus interface registers atm servicesar plus with xbr traffic management 14-42 mindspeed technologies ? 28236-DSH-001-B table 14-13. pci command register bit field size name description 15 ? 10 6 reserved set to 0x0b000000. 9 1 fb_en master fast back-to-back enable across target. 8 1 se_en serr* pin output enable. 7 1 reserved set to 0. 61 pe_en (1) parity error detection and report enable. 5 ? 3 3 reserved set to 0. 21 m_en (1) master enable. m_en must be asserted (that is, set to 1) before the cn8236 can act as master on the pci bus. 11 ms_en (1) memory space enable. ms_en must be asserted (that is, set to 1) before the cn8236 address space (registers and memory) can be accessed across the pci interface. 01 ? i/o space enable. (not used.) set to 0. note(s): (1) can be loaded from eeprom. table 14-14. pci status register bit field size name description 31 1 dpe parity error detected. 30 1 sse signalled system error. (device asserted serr*.) 29 1 rma received master abort. (device master aborted transfer.) 28 1 rta received target abort. (detected target abort as master.) 27 1 ? target aborted as slave. 26 ? 25 2 ? devsel speed (00 fast). 24 1 dpr reported data parity error. (parity error detected as master). 23 1 ? fast back-to-back supported as slave. set to 1. 22 1 ? udf support. set to 0. 21 1 ? 66 mhz support. set to 0. 20 1 new_cap capability list support. this bit indicates whether this function implements a list of extended capabilities defined in pci bus specification, revision 2.1, such as pci power management. when set to 1, indicates the presence of new capabilities. a value of 0 indicates that this function does not implement new capabilities. set to one. (1) 19 ? 16 4 reserved set to 0x0. note(s): (1) can be set to 0 from eeprom. cn8236 14.0 cn8236 registers atm servicesar plus with xbr traffic management 14.7 pci bus interface registers 28236-DSH-001-B mindspeed technologies ? 14-43 table 14-15. pci special status register bit field size name description 31 1 en_sid_wr enable svid/sid write. default = 0. 30 1 mstr_ctrl_swap (1) enable byte swapping on control words that the sar writes. default = low. 29 1 slave_swap (1) enable byte swapping on control words of a slave write or read access. default = low. 28 ? 23 6 reserved set to 0b000000. 22 ? 16 7 memory size mask (1) a 7-bit mask which sets one of a range of values for the size of the pci address space. default = 0000000. 0000000 = 8 m 15 ? 12 4 reserved set to 0. 11 1 intf_dis master interface disabled. if the m_en bit in the command field is a logic low, any attempt by the cn8236 to perform a dma transaction to the pci bus results in an error. intf_dis and merror bits set to a logic high. this bit can be reset by writing a logic high to itself. 10 1 int_fail master interface failed. set to a logic high when an internal pci/dma synchronization error has occurred. the merror bit is also set to a logic high. this bit can be reset by writing a logic high to itself. 9 1 merror memory error. indicates that the pci bus master has encountered a fatal error and therefore has halted operation. set when either rta, rma, dpr, intf_dis, or int_fail errors occur. this bit can be reset by writing a logic high to itself. 8 1 mrd error on master read/write. if a logic high, indicates that the errored transaction was a read, and the address of the read is located in the master_read_addr field. if a logic low, indicates the errored transaction was a write and the corresponding address is located in the master_write_addr field. 7 ? 0 8 reserved set to 0x00. note(s): (1) can be loaded from eeprom. table 14-16. eeprom register (1 of 2) bit field size name description 31 1 busy indicates that an eeprom operation is currently in progress. this bit must be read as a 0 before initiating an eeprom transfer. 14.0 cn8236 registers cn8236 14.7 pci bus interface registers atm servicesar plus with xbr traffic management 14-44 mindspeed technologies ? 28236-DSH-001-B 30 1 no_ack when set to a 1, indicates that the previous transfer failed (that is, no hardware address response). 29 ? 24 6 reserved reserved for future use. 23 ? 17 7 hardware_addr the 7-bit hardware address for a transfer that indicates the target of the transfer. the eeprom has the hardware address of b1010000. 16 1 read_write indicates the desired operation. 0 = write; 1 = read. 15 ? 8 8 byte_addr the desired byte address of the eeprom. 7 ? 0 8 data for writes, the data to be written to the eeprom. for reads, the data read from the eeprom. table 14-16. eeprom register (2 of 2) bit field size name description 28236-DSH-001-B mindspeed technologies ? 15-1 15 15.0 sar initialization?example tables the following tables provide an example cn8236 sar initialization of control registers, internal memory control structures, and external memory control structures. 15.1 segmentation initialization 15.1.1 segmentation control registers before segmentation is enabled, the host must allocate and initialize all of the segmentation control registers. table 15-1 lists the initialized values for each field. table 15-1. table of values for segmentation control register initialization (1 of 2) register field initialized value notes seg_ctrl (segmentation control register) seg_enable 0 ? 1 must be set to a logic low until initialization of all segmentation structures is complete. set to a logic high to commence segmentation process. seg_reset 0 use config0(global_reset) to initialize the sar. vbr_offset 0 schedule slot priority equals general priority. seg_gfc 0 disable segmentation gfc processing. dbl_slot 1 enable two word schedule slot entries. cbr_tun 1 enable cbr traffic scheduling. adv_abr_tmplt 1 enable per-connection mcr & icr abr parameters. tx_fifo_len 0x4 set transmit fifo buffer depth to four cells. clp0_eom 0 disable clp on eom processing. oam_stat_id 0x10 oam global status queue set to 16. seg_st_halt 0 disable status queue entry for a vcc halted with a partially segmented buffer. seg_ls_dis 0 enable local status queue full check. seg_hs_dis 0 enable host status queue full check. tx_rnd 1 round-robin transmit queue processing selected. tr_size 0x0 transmit queue size set to 64 entries. 15.0 sar initialization ? example tables cn8236 15.1 segmentation initialization atm servicesar plus with xbr traffic management 15-2 mindspeed technologies ? 28236-DSH-001-B 15.1.2 segmentation internal memory control structures before segmentation is enabled, the host must allocate and initialize all of the segmentation internal memory control structures. table 15-2 lists the initialized values for each field. seg_vbase (seg virtual channel connection base address register) seg_schb 0x1a5 schedule table starts at 0xd280 in sar-shared memory. seg_vccb 0x17d seg vcc table starts at 0xbe80 in sar-shared memory. seg_pmbase (seg pm base address register) seg_bckb 0x219 vbr bucket table starts at 0x10c80 in sar-shared memory. seg_pmb 0x1ad pm table starts at 0xd680 in sar-shared memory. seg_txbase (segmentation transmit queue base register) seg_txb 0x13d transmit queues start at 0x9e80 in sar-shared memory. xmit_interval 0x20 transmit queue update interval set to 32. tx_en 0x8 transmit queues 0 through 8 are enabled. table 15-1. table of values for segmentation control register initialization (2 of 2) register field initialized value notes table 15-2. table of values for segmentation internal memory initialization table field initialized value notes seg_sq_base table entry 0 (seg status queue base table entry 0) base_pntr 0x1c00 base address of status queue 0 is 0x1c00. local 0 status queue 0 resides in host memory. size 0x0 size of status queue 0 is 64 entries. write 0x0 must be initialized to 0. read_ud 0x0 must be initialized to 0. reserved 0x0 must be initialized to 0. seg_tq_base table entry 0 (seg transmit queue base table entry 0) read_ud_pntr 0x40 location of read_ud is at 0x100. local 0 read_ud located in host memory. update 0x0 must be initialized to 0. read 0x0 must be initialized to 0. reserved 0x0 must be initialized to 0. cn8236 15.0 sar initialization ? example tables atm servicesar plus with xbr traffic management 15.1 segmentation initialization 28236-DSH-001-B mindspeed technologies ? 15-3 15.1.3 segmentation sar shared memory control structures before segmentation is enabled, the host must allocate and initialize all of the segmentation sar-shared memory control structures. table 15-3 lists the initialized values for each field. table 15-3. table of values for segmentation sar shared memory initialization (1 of 2) table field initialized value notes seg vcc table entry 0 ? (words 0 ? 6) pm_index 0x0 pm table index = 0. last_pntr 0x0 must be initialized to 0. atm_header 0x00100100 atm header, vpi = 0x1, vci = 0x10. crc_rem 0xffff_ffff must be initialized to 0xffff_ffff for aal5 channels. betag 0 first aal3/4 btag/etag pair is 0. sn 0 first aal3/4 sn = 0. mid 5 aal3/4 mid = 5. stm_mode 0 status message mode enabled. stat 0x2 channel uses status queue 2. pm_en 1 pm oam processing enabled. curr_pntr 0x0 must be initialized to 0. vpc 0 vcc connection. gfr_pri 0x2 gfr ubr priority is 2. sch_mode 0x4 channel configured for vbr traffic. pri 0x3 schedule priority is 3. sch_opt 1 send maximum burst. reserved 0x0 must be initialized to 0. seg buffer descriptors (no initialization required.) seg transmit queue entries vld 0 must be initialized to 0. link_head 0 must be initialized to 0. fnd_chain 0 must be initialized to 0. seg_bd_pntr 0x0 must be initialized to 0. reserved 0x0 must be initialized to 0. 15.0 sar initialization ? example tables cn8236 15.1 segmentation initialization atm servicesar plus with xbr traffic management 15-4 mindspeed technologies ? 28236-DSH-001-B seg status queue entries user_pntr 0x0 must be initialized to 0. vld 0 must be initialized to 0. stop 0 must be initialized to 0. done 0 must be initialized to 0. single 0 must be initialized to 0. ovfl 0 must be initialized to 0. i_exp 0x0 must be initialized to 0. i_man 0x0 must be initialized to 0. seg_vcc_index 0x0 must be initialized to 0. reserved 0x0 must be initialized to 0. seg_pm table entry 0 atm_header 0x00100108 vpi = 0x1, vci = 0x10, pti = 4 (f5 segment). fwd_tuc0 0x0 must be initialized to 0. fwd_tuc01 0x0 must be initialized to 0. bck_msn 0x0 must be initialized to 0. bck_tuc0 0x0 must be initialized to 0. bck_tuc01 0x0 must be initialized to 0. trcc0 0x0 must be initialized to 0. trcc0+1 0x0 must be initialized to 0. bip 0x0 must be initialized to 0. fwd_mon 1 forward monitoring cell generation enabled. block_size 10 pm oam block size of 512. fwd_msn 0x3 initial sequence number is 3. reserved 0x0 must be initialized to 0. table 15-3. table of values for segmentation sar shared memory initialization (2 of 2) table field initialized value notes cn8236 15.0 sar initialization ? example tables atm servicesar plus with xbr traffic management 15.2 scheduler initialization 28236-DSH-001-B mindspeed technologies ? 15-5 15.2 scheduler initialization 15.2.1 scheduler control registers before segmentation is enabled, the host must allocate and initialize all of the scheduler control registers. table 15-4 lists the initialized values for each field. table 15-4. table of values for scheduler control register initialization register field initialized value notes sch_pri (schedule priority register) tun_ena7-0 0 no tunnels enabled. gfc7-0 0 no gfc priorities enabled. qpcr_ena7-0 0x04 enable pcr limits on queue 2. sch_size (schedule size register) tbl_size 0x80 schedule table consists of 128 entries. slot_per 0x5b schedule slot period is 91 sysclk periods. sch_abr_max (schedule maximum abr register) vcc_max 0x63 enable 50 channels of abr processing. pcr_que_int01 (pcr queue interval 0 and 1 register) qpcr_int0 0x0 not used since only one global pcr queue enabled. qpcr_int1 0x0 not used since only one global pcr queue enabled. pcr_que_int_23 (pcr queue interval 2 and 3 register) qpcr_int2 0x0 not used since only one global pcr queue enabled. qpcr_int3 0x16c pcr interval = 364 schedule slots. sch_abr_con (schedule abr constant register) abr_trm 0x23c set trm to tm 4.1 default of 100 ms. abr_adtf 0xb2e set adtf to tm 4.1 default of 0.5 second. sch_abrbase (abr decision table lookup base reg) oor_ena 1 enable out-of-rate abr rm cells. oor_int 0x1c9d produces an out-of-rate interval of one cell per second. sch_abrb 0x1d1 abr table starts at 0xe880 in sar-shared memory. sch_cng (abr congestion register) fbq_cng 0x0 no congestion experienced. 15.0 sar initialization ? example tables cn8236 15.2 scheduler initialization atm servicesar plus with xbr traffic management 15-6 mindspeed technologies ? 28236-DSH-001-B 15.2.2 scheduler internal memory control structures no internal memory scheduler structures need to be initialized. 15.2.3 scheduler sar shared memory control structures before segmentation is enabled, the host must allocate and initialize all of the scheduler sar-shared memory control structures. table 15-5 lists the initialized values for each field. table 15-5. table of values for sch sar shared memory initialization (1 of 2) table field initialized value notes schedule table (cbr slot) cbr 1 slot will schedule a cbr channel. cbr_vcc_index 0x0 schedule seg_vcc_index = 0 channel as cbr. reserved 0xf set all reserved bits to 1. schedule table (tunnel slot) cbr 0 slot will schedule a tunnel. pri 0x3 tunnel priority queue = 3. reserved 0xf set all reserved bits to 1. schedule table (default) reserved 0xf set all reserved bits to 1. seg vcc table entry for vbr (words 7 ? 8) bucket2 0x4 offset of four into bucket table for vbr2 parameters. l1_exp 0xb ? l1_man 0x0 gcra l = 2. i1_exp 0xb ? i1_man 0x100 gcra i = 3. reserved 0x0 must be initialized to 0. bucket table entry l2_exp 0xa ? l2_man 0x0 gcra l = 1. i2_exp 0xb ? i2_man 0x0 gcra i = 2. reserved 0x0 must be initialized to 0. seg vcc table entry for gfr (words 7 ? 9) (note: set pri_gfr lower than pri in word 6). mcrlim_idx 0x3 offset of 3 into gfr mcr_limit table. l1_exp 0xf ? l1_man 0x0 gcra l = 32. i1_exp 0xf ? i1_man 0x120 gcra i = 50. (provides mcr ~ 3 mbps.) reserved 0x0 must be initialized to 0. cn8236 15.0 sar initialization ? example tables atm servicesar plus with xbr traffic management 15.2 scheduler initialization 28236-DSH-001-B mindspeed technologies ? 15-7 seg vcc table entry for abr (words 7 ? 19) cong_id 0x1 channel associated with rsm free buffer queue 1 for host congestion indication. oor_pri 0x2 out-of-rate rm cells assigned to priority queue 2. crm 0x14 tm 4.1 crm parameter set to 20. mcr_index ? output of abr template. icr_index ? output of abr template. fwd_id 0x01 forward rm cell id field set to 1. fwd_dir 0 forward rm cell dir field set to 0. fwd_bn 0 forward rm cell bn field set to 0. fwd_ci 0 forward rm cell ci field set to 0. fwd_ni 0 forward rm cell ni field set to 0. fwd_ra 0 forward rm cell ra field set to 0. fwd_er 0x64bf forward rm cell er field set to approximately 360000 cells per second. reserved 0x0 must be initialized to 0. (all other fields) ? direct output of abr template. abr cell decision block (all fields) ? direct output of abr template. abr rate decision block (all fields) ? direct output of abr template. exponent table (all fields) ? direct output of abr template. table 15-5. table of values for sch sar shared memory initialization (2 of 2) table field initialized value notes 15.0 sar initialization ? example tables cn8236 15.3 reassembly initialization atm servicesar plus with xbr traffic management 15-8 mindspeed technologies ? 28236-DSH-001-B 15.3 reassembly initialization 15.3.1 reassembly control registers before reassembly is enabled, the host must allocate and initialize all of the reassembly control registers. table 15-6 lists the initialization values for each field. table 15-6. table of values for reassembly control register initialization (1 of 2) register field initialized value notes rsm_ctrl0 (reassembly control register 0) rsm_enable 0 ? 1 must be set to a logic low until initialization of all reassembly structures is complete. set to a logic high to commence reassembly process. rsm_reset 0 use config0(global_reset) to initialize the sar. vpi_mask 1 uni vpi space selected. rsm_phalt 0 rsm halt on receive parity error disabled. fwall_en 1 firewall function enabled. rsm_fbq_dis 0 free buffer queue underflow protection enabled. rsm_stat_dis 0 status queue overflow protection enabled. gto_en 1 enable internal time-out interrupt. max_len 0x10 aal5 max cpcs-pdu length = 16384 bytes. gdpri 0x4 global service discard priority = 4. reserved 0x0 must be initialized to 0. rsm_ctrl1 (reassembly control register 1) oam_ff_dsc 1 oam cells discarded when incoming dma fifo buffer almost full. oam_en 1 oam detection enabled. oam_qu_en 1 global oam fb and stat queues enabled. oam_bfr_qu 0x4 global oam free buffer queue = 4. oam_stat_qu 0x4 global oam status queue = 4. reserved 0x0 must be initialized to 0. rsm_fqbase (rsm free buffer queue base register) fbq1_base 0xb0 free buffer queue bank 1 starts at 0x5800 in sar-shared memory. fbq0_base 0x30 free buffer queue bank 0 starts at 0x1800 in sar-shared memory. cn8236 15.0 sar initialization ? example tables atm servicesar plus with xbr traffic management 15.3 reassembly initialization 28236-DSH-001-B mindspeed technologies ? 15-9 rsm_fqctrl (rsm free buffer queue control register) fbq_size 0x0 free buffer queue size is 64 entries. fwd_rnd 1 free buffer queues are processed in round-robin fashion for credit return. fbq0_rtn 0 free buffer queue bank 0 selected for buffer return processing. fwd_en 0x4 free buffers queues 0 through 4 enabled for buffer return processing. fbq_ud_int 0x20 free buffer queue update interval set to 32. reserved 0x0 must be initialized to 0. rsm_tbase (rsm table base register) rsm_vccb 0x105 rsm vcc table starts at 0x8280 in sar-shared memory. rsm_itb 0xf0 vpi index table starts at 0x7800 in sar-shared memory. rsm_to (rsm time-out register) rsm_to_per 0x100 internal time-out interrupt every 256 sysclk periods. rsm_to_cnt 0x10 rsm vcc table entries 0 through 16 enabled for time-out processing. rs_qbase (rsm/seg queue base register) rs_size 0x0 rsm/seg queue size is 256 entries. rs_qbase 0x12d rsm/seg queue starts at 0x9680 in sar-shared memory. reserved 0x0 must be initialized to 0. table 15-6. table of values for reassembly control register initialization (2 of 2) register field initialized value notes 15.0 sar initialization ? example tables cn8236 15.3 reassembly initialization atm servicesar plus with xbr traffic management 15-10 mindspeed technologies ? 28236-DSH-001-B 15.3.2 reassembly internal memory control structures before reassembly is enabled, the host must allocate and initialize all of the reassembly internal memory control structures. table 15-7 lists the initialized values for each field. table 15-7. table of values for reassembly internal memory initialization table field initialized value notes rsm_sq_base table entry 0 (rsm status queue base table entry 0) base_pntr 0x1800 base address of rsm status queue 0 is 0x6000. local 0 status queue 0 resides in host memory. size 0x0 size of status queue 0 is 64 entries. write 0x0 must be initialized to 0. read_ud 0x0 must be initialized to 0. reserved 0x0 must be initialized to 0. rsm_fbq_base table entry 0 (rsm free buffer queue base table entry 0) read_ud_pntr 0x0 location of read_ud is at 0x0. bd_local 0 buffer descriptors and read_ud located in host memory. bfr_local 0 buffers located in host memory. empt 0 must be initialized to 0. update 0x0 must be initialized to 0. read 0x0 must be initialized to 0. forward 0x20 32 free buffers initially put on free buffer queue. length 0x200 buffer lengths in free buffer queue 0 are 200 bytes. reserved 0x0 must be initialized to 0. global time-out table term_tocnt0 0x400 provides a 133 ms time-out period. term_tocnt1 0xffff provides an 8.5 sec time-out period. term_tocnt2 0x400 provides a 133 ms time-out period. term_tocnt3 0x400 provides a 133 ms time-out period. term_tocnt4 0x400 provides a 133 ms time-out period. term_tocnt5 0x400 provides a 133 ms time-out period. term_tocnt6 0x400 provides a 133 ms time-out period. term_tocnt7 0x400 provides a 133 ms time-out period. to_vcc_index 0x0 must be initialized to 0. reserved 0x0 must be initialized to 0. cn8236 15.0 sar initialization ? example tables atm servicesar plus with xbr traffic management 15.3 reassembly initialization 28236-DSH-001-B mindspeed technologies ? 15-11 15.3.3 reassembly sar shared memory control structures before reassembly is enabled, the host must allocate and initialize all of the reassembly sar-shared memory control structures. table 15-8 lists the initialized values for each field. table 15-8. table of values for reassembly sar shared memory initialization (1 of 4) table field initialized value notes vpi index table entry 0 vp_en 1 vpi = 0 enabled. note: all entries in the vpi index table must be initialized. if vpi is disabled, set vp_en = 0. vci_range 0x10 allowable vci range is 0 to 0x43f. vci_it_pntr 0x2014 vci index table is located at 0x8050 in sar-shared memory. vci index table entry 0 vcc_block_pntr 0x0 initial block of 64 vcc table entries is 0. reserved 0x0 must initialized to 0. rsm vcc table entry 0 ff_dsc 1 enable fifo buffer full epd. vc_en 1 table entry is enabled. all vcc table entries that have a path through the vpi/vci lookup space must be initialized. if entry is disabled, set vc_en = 0. aal_type 0x0 channel configured for aal5. dpri 0x2 channel service discard priority set to 2. to_index 0x1 point to term_tocnt1 global time-out value. pm_index 0x2 channel used entry 2 of pm_oam table. aal_en 0x082 message status mode and frame relay discard enabled. to_last 0 not last vcc entry processed for time-out. rsm vcc table entry 0 to_en 1 time-out processing enabled on this channel. cur_tocnt 0x0 must be initialized to 0. abr_ctrl 0x0 no abr service enabled on this channel. pdu_flags 0x002 must be initialized to 2. tot_pdu_len 0x0 must be initialized to 0. crc_rem 0xffff_ffff must be initialized to 0xffff_ffff for aal5 channels. basize 0x0 must be initialized to 0. (for aal3/4 only.) next_st 0x2 must be initialized to 2. (for aal3/4 only.) next_sn 0x0 must be initialized to 0. (for aal3/4 only.) 15.0 sar initialization ? example tables cn8236 15.3 reassembly initialization atm servicesar plus with xbr traffic management 15-12 mindspeed technologies ? 28236-DSH-001-B rsm vcc table entry 0 btag 0x0 must be initialized to 0. (for aal3/4 only.) stat 0x1 channel uses status queue 1. bfr1 0x11 channel uses free buffer queue 17 for com buffers. bfr0 0x1 channel uses free buffer queue 1 for bom buffers. seg_vcc_index 0x4 corresponding seg channel = 4 for pm_oam and abr service. serv_dis 0x0 must be initialized to 0. rx_counter 0x100 initial firewall credit = 256. reserved 0x0 must be initialized to 0. rsm aal3/4 head vcc table entry vc_en 1 table entry is enabled. aal_type 0x2 channel configured for aal3/4. ff_dsc 1 enable fifo buffer full epd. pm_index 0x2 channel used entry 2 of pm_oam table. aal_en 0x084 enable buffer descriptor linking. to_last 0 not last vcc entry processed for time-out. to_en 0 must be initialized to 0. mid0 1 allow mid value of 0. mid_bits 0x5 allow mid values up to 31. crc10_en 1 enable crc10 field checking and error counting. li_en 1 enable li field checking and error counting. st_en 1 enable st field checking and error counting. sn_en 1 enable sn field checking and error counting. cpi_en 1 enable cpi field checking. bat_en 1 enable basize = length checking. bah_en 0 do not check for basize < 37. er_efci 0 must be initialized to 0. table 15-8. table of values for reassembly sar shared memory initialization (2 of 4) table field initialized value notes cn8236 15.0 sar initialization ? example tables atm servicesar plus with xbr traffic management 15.3 reassembly initialization 28236-DSH-001-B mindspeed technologies ? 15-13 rsm aal3/4 head vcc table entry abr_ctrl 0x0 no abr service enabled on this channel. vcc_index 0x0010 aal3/4 block located at vcc table entry #16. stat 0x1 oams use status queue 1. bfr1 ? (not applicable.) bfr0 0x1 oams use free buffer queue 1. crc10_err 0 must be initialized to 0. mid_err 0 must be initialized to 0. li_err 0 must be initialized to 0. sn_err 0 must be initialized to 0. bom_ssm_err 0 must be initialized to 0. eom_err 0 must be initialized to 0. seg_vcc_index 0x4 corresponding seg channel = 4 for pm_oam and abr service. rx_counter/vpc_ index 0x100 initial firewall credit = 256. rsm buffer descriptors next_ptr 0x0 initialization optional. buff_pntr 0x2000 buffer address of 0x2000. rsm free buffer queue entries vld 0 ? 1 free buffer queue can be initialized with several free buffers. valid entries should have vld = 1, and invalid entries should have vld = 0. buffer_pntr 0x2000 buffer address of 0x2000. bd_pntr 0x80 buffer descriptor address of 0x80. fwd_vld 0 must be initialized to 0. vcc_index 0 must be initialized to 0. reserved 0x0 must be initialized to 0. rsm status queue entries vld 0 must be initialized to 0. (all other entries) 0 must be initialized to 0. lecid table lecid0-31 0x20 lane lecid = 32. table 15-8. table of values for reassembly sar shared memory initialization (3 of 4) table field initialized value notes 15.0 sar initialization ? example tables cn8236 15.3 reassembly initialization atm servicesar plus with xbr traffic management 15-14 mindspeed technologies ? 28236-DSH-001-B rsm_pm table entry 0 bcnt 0x0 must be initialized to 0. bip16 0x0 must be initialized to 0. msn 0x4 first expected msn in forward monitoring cell is four. reserved 0x0 must be initialized to 0. trcc0 0x0 must be initialized to 0. trcc01 0x0 must be initialized to 0. table 15-8. table of values for reassembly sar shared memory initialization (4 of 4) table field initialized value notes cn8236 15.0 sar initialization ? example tables atm servicesar plus with xbr traffic management 15.4 general initialization 28236-DSH-001-B mindspeed technologies ? 15-15 15.4 general initialization 15.4.1 general control registers before the sar is enabled, the host must allocate and initialize all of the general sar control registers. table 15-9 lists the initialized values for each field. table 15-9. table of values for general control register initialization (1 of 2) register field initialized value notes config0 (configuration register 0) lp_enable 0 local processor not used. global_reset 0 ? 1 this must be toggled to a logic high and back to a logic low after completion of all initialization, but before rsm and seg coprocessors are enabled. pci_mstr_reset 0 use global_reset to reset sar. pci_err_reset 0 must be initialized to 0. int_lbank 0 ? 1 should be set to 0 during initialization, but set to one after system reset. pci_read_multi 1 pci read multiple command used. pci_arb 1 round-robin arbitration of internal read/write pci master. statmode 0x0 selects bom sync hardware mode. fr_rmode 0 early rsm header processing enabled. fr_loop 0 internal atm physical interface disabled. utopia_mode 1 cell handshake mode selected. lp_bwait 0 selects 0 wait states between consecutive data cycles during local processor. memctrl 0 selects 0 wait states sar-shared memory. banksize 0x3 512 kb banks selected. divider 0x0 divide by 128 selected for clock prescaler. reserved 0x0 must be initialized to 0. int_delay (interrupt delay register) timer_loc 0 interrupt hold-off timer used with hint*. en_timer 0 disable status queue interrupt timer delay. en_stat_cnt 1 enable status queue interrupt counter delay. stat_cnt[7:0] 0x35 interrupt delay counter set to 53. 15.0 sar initialization ? example tables cn8236 15.4 general initialization atm servicesar plus with xbr traffic management 15-16 mindspeed technologies ? 28236-DSH-001-B host_st_wr (host status write register) rsm_hs_write ? read twice after sar reset. rsm_ls_write ? read twice after sar reset. host_istat1 (host interrupt status register 1) (all) ? read twice host_st_wr reset. host_istat0 (host interrupt status register 0) (all) ? read twice host_istat1 reset. lp_istat1 (local interrupt status register 1) (all) ? read twice sar reset. lp_istat0 (local interrupt status register 0) (all) ? read twice lp_istat1 reset. host_imask1 (host interrupt mask register 1) (all) 0x8700fc07 enable all errors to cause an interrupt. host_imask0 (host interrupt mask register 0) (all) 0x4040000f enable interrupts in errors, counter relievers and framer interrupt. lp_imask1 (local interrupt mask register 1) (all) 0x0 local processor not used. lp_imask0 (local interrupt mask register 0) (all) 0x0 local processor not used. pci configuration space command 0x0346 enable all functions of pci interface. lat_timer 0x10 latency timer = 16 clock periods. base_address_ register_0 0x01 base address of sar device in pci memory space is 0x0100_0000. interrupt_line 0x00 interrupt vector = 0. (all other fields) ? hard-coded reads only. pci command register fb_en 1 enable master fast back-to-back across target. se_en 1 enable serr* output pin. pe_en 1 enable parity error detection and report. m_en 1 enable cn8236 device master on the pci bus. ms_en 1 enable cn8236 memory space access across the pci bus. pci status register ?? (no initialization required.) pci special_status register ?? (no initialization required.) pci eeprom register ?? (no initialization required.) table 15-9. table of values for general control register initialization (2 of 2) register field initialized value notes 28236-DSH-001-B mindspeed technologies ? 16-1 16 16.0 electrical and mechanical specifications 16.1 timing 16.1.1 pci bus interface timing all pci bus interface signals are synchronous to the pci bus clock, hclk, except for hrst* and hint*. table 16-1 provides the pci bus interface timing parameters. figures 16-1 and 16-2 illustrate this timing. table 16-1. pci bus interface timing parameters (1 of 2) symbol parameter min max units t cyc hclk cycle time (1) 25 ? ns t high hclk high time (1) 10 15 ns t low hclk low time (1) 10 15 ns t su had input setup time to hclk (1) 7 ? ns hc/be input setup time to hclk (1) 7 ? ns hpar input setup time to hclk (1) 7 ? ns hframe* input setup time to hclk (1) 7 ? ns hirdy* input setup time to hclk (1) 7 ? ns htrdy* input setup time to hclk (1) 7 ? ns hstop* input setup time to hclk (1) 7 ? ns hdevsel* input setup time to hclk (1) 7 ? ns hidsel input setup time to hclk (1) 7 ? ns hgnt* input setup time to hclk (1) 10 ? ns hperr* input setup time to hclk (1) 7 ? ns t h input hold time from hclk ? all inputs (1) 0 ? ns 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-2 mindspeed technologies ? 28236-DSH-001-B t val hclk to had valid delay (2) 211ns hclk to hc/be valid delay (2) 211ns hclk to hpar valid delay (2) 211ns hclk to hframe* valid delay (2) 211ns hclk to hirdy* valid delay (2) 211ns hclk to hstop* valid delay (2) 211ns hclk to hdevsel valid delay (2) 211ns hclk to hperr* valid delay (2) 211ns hclk to hreq valid delay (2) 212ns hclk to hserr* valid delay (2) 211ns hclk to stat valid delay (3) 220ns t on float to active delay ? all three-state outputs (2) 2 ? ns t off active to float delay ? all three-state outputs (2) ? 23 ns t rst-off reset active to output float delay ? 40 ns note(s): (1) see figure 16-1 for waveforms and definitions. (2) see figure 16-2 for waveforms and definitions. the maximum output delays are measured with a 50 pf load, and the minimum delays are measured with a 0 pf load. (3) applicable when stat outputs configured as bom cell synchronization signals. table 16-1. pci bus interface timing parameters (2 of 2) symbol parameter min max units figure 16-1. pci bus input timing measurement conditions hclk input t low t high t cyc t su t h 8236_078 cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-3 figure 16-2. pci bus output timing measurement conditions hclk output delay three-state output t val t on t off 8236_079 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-4 mindspeed technologies ? 28236-DSH-001-B 16.1.2 atm physical interface timing ? utopia and slave utopia all atm physical interface signals are synchronous to interface clocks, rxclk and/or txclk, except for txclav and rxclav in the slave utopia mode. timing parameters for the utopia interface are provided in table 16-2 . table 16-3 provides the timing parameters for the slave utopia interface. timing diagrams for both interfaces are provided in figures 16-3 and 16-4 . table 16-2. utopia interface timing parameters symbol parameter min max units t cyc rxclk/txclk cycle time (1) 20 ? ns t high rxclk/txclk high time (1) (% of tcyc) 40 60 % t low rxclk/txclk low time (1) (% of tcyc) 40 60 % t su rxdata input setup time to rxclk (1) 4 ? ns rxpar input setup time to rxclk (1) 4 ? ns rxsoc input setup time to rxclk (1) 4 ? ns rxclav input setup time to rxclk (1) 4 ? ns txclav input setup time to txclk (1) 4 ? ns t h rxdata input hold time from rxclk (1) 1 ? ns rxpar input hold time from rxclk (1) 1 ? ns rxsoc input hold time from rxclk (1) 1 ? ns rxclav input hold time from rxclk (1) 1 ? ns txclav input hold time from txclk (1) 1 ? ns t val txclk to txdata valid delay (2) 212ns txclk to txpar valid delay (2) 212ns txclk to txsoc valid delay (2) 212ns txclk to txen* valid delay (2) 212ns rxclk to rxen* valid delay (2l 212ns note(s): (1) see figure 16-3 for waveforms and definitions. (2) see figure 16-4 for waveforms and definitions. the output delays are measured with a 50 pf load. cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-5 table 16-3. slave utopia interface timing parameters symbol parameter min max units t cyc rxclk/txclk cycle time (1) 20 ? ns t high rxclk/txclk high time (1) (% of tcyc) 40 60 % t low rxclk/txclk low time (1) (% of tcyc) 40 60 % t su rxdata input setup time to rxclk (1) 4 ? ns rxpar input setup time to rxclk (1) 4 ? ns rxsoc input setup time to rxclk (1) 4 ? ns rxen* input setup time to rxclk (1) 4 ? ns txen* input setup time to txclk (1) 4 ? ns t h rxdata input hold time from rxclk (1) 1 ? ns rxpar input hold time from rxclk (1) 1 ? ns rxsoc input hold time from rxclk (1) 1 ? ns rxen* input hold time from rxclk (1) 1 ? ns txen* input hold time from txclk (1) 1 ? ns t val txclk to txdata valid delay (2) 212ns txclk to txpar valid delay (2) 212ns txclk to txclav valid delay (2) 212ns rxclk to rxclav valid delay (2) 212ns txclk to txsoc valid delay (2) 212ns note(s): (1) see figure 16-3 for waveforms and definitions. (2) see figure 16-4 for waveforms and definitions. the output delays are measured with a 50 pf load. figure 16-3. utopia and slave utopia input timing measurement conditions rxclk input t low t high t cyc t su t h 8236_080 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-6 mindspeed technologies ? 28236-DSH-001-B figure 16-4. utopia and slave utopia output timing measurement conditions txclk output delay t val 8236_081 cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-7 16.1.3 system clock timing the system clock timing consists of the clk2x input and the sysclk and clkd3 outputs. the clk2x input and sysclk outputs are used to generate the internal and external system clocks, sar-shared memory, and processor read and write timing. the clkd3 output can be used as the atm physical interface clock. there is no defined skew relationship between the clk2x input and sysclk and clkd3 outputs. table 16-4 specifies the timing parameters of the three clocks. figures 16-5 and 16-6 illustrate this timing. table 16-4. system clock timing symbol parameter min max units input clocks (1 ) t cf clk2x frequency 0 66 mhz t c clk2x period 15.15 ns t cd clk2x duty cycle 40 60 % t cr clk2x rise time 0 6 ns t cf clk2x fall time 0 6 ns output clocks (2) t sf sysclk frequency t cf /2 mhz t s sysclk period 2t c ns t sh sysclk high time (t s /2) ? 2(t s /2) + 2 ns t sl sysclk low time (t s /2) ? 2(t s /2) + 2 ns t sr sysclk rise time 1 4 ns t sf sysclk fall time 1 4 ns t df clkd3 frequency t cf /3 mhz t d clkd3 period 3t c t dh clkd3 high time (t d /2) ? 2(t d /2) + 2 ns t dl clkd3 low time (t d /2) ? 2(t d /2) + 2 ns t dr clkd3 rise time 1 4 ns t df clkd3 fall time 1 4 ns note(s): (1) see figure 16-5 for waveforms and definitions. (2) see figure 16-6 for waveforms and definitions. the outputs are measured with a load of 35 pf. 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-8 mindspeed technologies ? 28236-DSH-001-B figure 16-5. input system clock waveform t cr t cf 2.0 v 1.5 v 0.8 v t c 8236_082 figure 16-6. output system clock waveform t sr, t dr t sf, t df 2.4 v 1.5 v 0.4 v t sh, t dh t sl, t dl t s, t d 8236_083 cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-9 16.1.4 cn8236 memory interface timing memory access times and other timing requirements are specified at three typical implementations of one, two, and four banks of by_8 sram. table 16-5 lists the number of loads per bank for the different sram organizations, while table 16-6 lists the capacitive loading used in the timing specifications given for the three typical implementations. cn8236 memory interface timing is provided in table 16-7 . (see section 9.2 , for details of memory bank organization.) table 16-5. sram organization loading dependencies signal loads/bank (1) by_16 sram by_8 sram by_4 sram laddr[18:0] (1) 248 ldata[31:0] (1) 111 mwr* (1) 2n/an/a moe* (1) 248 mcsx* (1, 2) 248 mwex* (1) 112 note(s): (1) typical input loading for sram is 7 pf. for exact values, consult the sram databook. (2) only connected to one bank by definition. table 16-6. sar shared memory output loading conditions signal 4 banks of by_8 sram 2 banks of by_8 sram 1 bank of by_8 sram units memory interface loading (1) laddr[18:0] (1) 150 100 50 pf moe* 150 100 50 pf mwr* (2) ? 50 35 pf ldata[31:0] 50 35 25 pf mwe[3:0]* 50 35 25 pf mcs[3:0]* 50 35 25 pf note(s): (1) in general, the laddr loading is the most critical parameter. one bank of by_8 sram has the same address loading as two banks of by_16 and 1/2 bank of by_4 sram. for example, use the timing from the two banks of by_8 column for four banks of by_16 sram, or one bank of by_4 sram. (2) for by_16 sram, the we* input has the same loading as the address bus and oe*; therefore, 16 loads specified by the four banks of by_8 is not applicable, since the maximum number of by_16 srams supported is eight. 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-10 mindspeed technologies ? 28236-DSH-001-B table 16-7. cn8236 memory interface timing symbol parameter 4 banks of by_8 sram 2 banks of by_8 sram 1 bank of by_8 sram units min max min max min max memory read timing t rc read cycle time (2) t ? t ? t ? ns t aov laddr[18:0] output valid (1) 1101 8 1 7ns t mcsov mcs[3:0]* output valid (1) 1101 8 1 7ns t mweov mwe* byte enables output valid (1) (rammode = 1) 1101 8 1 7ns t moel moe* low (1) ? 17 ? 16 ? 15 ns t moeh moe* high (1) ? 10 ? 8 ? 7ns t dod ldata output disable (1) ? 7 ? 6 ? 6ns t dis ldata input setup (1) 5 ? 5 ? 5 ? ns t dh ldata input hold (1) 0 ? 0 ? 0 ? ns t doe ldata driven by sar (1) 12 ? 11 ? 11 ? ns t dodmoe ldata disable to moe* low (1) 0 ? 0 ? 0 ? ns t moedoe moe* high to ldata driven (1) 6 ? 7 ? 8 ? ns memory write timing t wc write cycle time (2) t ? t ? t ? ns t w mwr*, mwe[3:0]* width (2, 4) t/2-2 ? t/2 ? 2 ? t/2 ? 2 ? ns t aov laddr[18:0] output valid (4) 1101 8 1 7ns t mcsov mcs[3:0]* output valid (4) 1101 8 1 7ns t mweov mwe* byte enables output valid (1) (rammode = 1) 1101 8 1 7ns t dov ldata output valid ( 4) 110110110ns t mwel mwe[3:0]* low (4) t/2 ? 216 ? 16 ? 16 ns t mweh mwe[3:0]* high (4) ? 1 ? 1 ? 1ns t mwrl mwr[3:0]* low ( 4) t/2 ? 216 ? 16 ? 16 ns t mwrh mwr[3:0]* high (4) ? 1 ? 1 ? 1ns note(s): (1) see figure 16-7 for waveforms. (2) t = t s for single cycle memory (no wait states), t = 2t s for 2-cycle memory, (1 wait state). (3) insert 1 clock cycle for 2-cycle memory (1 wait state). (4) see figure 16-8 for waveforms. 5. sysclk shown for reference only. cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-11 figure 16-7. cn8236 memory read timing laddr mwe[3:0]* be* moe* mcs[3:0]* t aov (max) sysclk t aov (min) t mcsov mweov(max) mweov(min) (max) t mcsov (min) t moel t dod t dis t dh t t moeh moedoe sram data valid valid valid (1) ldata t dodmoe t t valid t doe (2) mwe* mwr* 8236_117 note(s): (1) insert one clock cycle for two cycle memory (one wait state). (2) sysclk shown for reference only. 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-12 mindspeed technologies ? 28236-DSH-001-B figure 16-8. cn8236 memory write timing laddr ldata mwe[3:0]* mcs[3:0]* t aov (max) sysclk t aov (min) t mcsov (max) t mcsov (min) t mweov (max) t mweov (min) t mwel t mweh valid valid valid (1) mwr* t mwrl t mwrh t dov (max) t dov (min) tw valid (2) mwe[3:0]* be* 8236_085 note(s): (1) insert 1 clock cycle for 2-cycle memory (1 wait state). (2) sysclk shown for reference only. cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-13 16.1.5 phy interface timing (standalone mode) the standalone mode of operation is entered when the procmode input is at a logic high indicating that no local processor is present. in this mode, the cn8236 changes its memory map to include the atm physical interface device. the interface is fully synchronous to sysclk and is designed to interface directly to the rs825x atm receiver/transmitter. timing is provided in table 16-8 and figures 16-9 and 16-10 . (see section 10.6 for details.) table 16-8. phy interface timing (procmode = 1) symbol parameter min max units synchronous inputs t is pwait* input setup (1) 14 ? ns ldata input setup (1) 5 ? ns t ih pwait* input hold (1) 0 ? ns ldata input hold (1) 0 ? ns synchronous outputs t ov prdy* output valid delay (2) 515ns pas output valid delay (2) 515ns pcs* output valid delay (2) 515ns pblast* output valid delay (2) 515ns pwnr output valid delay (2) 515ns ldata* output valid delay (2) 110ns laddr output valid delay (2) 110ns note(s): (1) see figure 16-9 for waveforms and definitions. (2) see figure 16-10 for waveforms and definitions. the outputs are measured with a load of 35 pf. figure 16-9. synchronous phy interface input timing t ih sysclk sync input t is 8236_115 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-14 mindspeed technologies ? 28236-DSH-001-B 16.1.6 local processor interface timing timing for the local processor interface can be broken into two sections. the first is the synchronous-to-sysclk interface of processor control signals to and from the cn8236. the second is the interface to the sar-shared memory and the cn8236 control and status registers, which involves both sram and transceiver, and buffer timing parameters that are not specified and are left up to the system designer. all of the synchronous interface signals are inputs to the cn8236 except for sysclk and the ready output of the cn8236 (prdy*). the output loading of these signals is 35 pf for the timing provided in table 16-9 . synchronous processor interface timing is provided in figures 16-11 and 16-12 . memory interface timing is provided in table 16-10 . local interface processor and interfacing timing is provided in figures 16-13 and 16-14 . figure 16-10. synchronous phy interface output timing t ov (min) sysclk sync output t ov (max) t ov (min) t ov (max) valid valid 8236_116 table 16-9. synchronous processor interface timing (1 of 2) symbol parameter min max units synchronous inputs t is pcs* input setup (1) 8 ? ns pas* input setup (1) 10 ? ns pblast* input setup (1) 10 ? ns pwait* input setup (1) 10 ? ns paddr[1,0] input setup (1) 10 ? ns pbsel[1,0] input setup (1) 8 ? ns pbe[3:0]* input setup (1) 8 ? ns pwnr input setup (1) 10 ? ns cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-15 t ih pcs* input hold (1) 0 ? ns pas* input hold (1) 0 ? ns pblast* input hold (1) 0 ? ns pwait* input hold (1) 0 ? ns paddr[1,0] input hold (1) 0 ? ns pbsel[1,0] input hold (1) 0 ? ns pbe[3:0]* input hold (1) 0 ? ns pwnr input hold (1) 0 ? ns synchronous outputs t ov prdy* output valid delay (2) 515ns note(s): (1) see figure 16-11 for waveforms and definitions. (2) see figure 16-12 for waveforms and definitions. the outputs are measured with a load of 35 pf. table 16-9. synchronous processor interface timing (2 of 2) symbol parameter min max units figure 16-11. synchronous local processor input timing t ih sysclk sync input t is 8236_086 figure 16-12. synchronous local processor output timing t ov (min) sysclk sync output t ov (max) t ov (min) t ov (max) valid valid 8236_087 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-16 mindspeed technologies ? 28236-DSH-001-B table 16-10. local processor memory interface timing symbol parameter min max units t pdaenl sysclk to pdaen* low, bus recovery cycle (1 ) ? 12 ns t pdaenh sysclk to pdaen* high, bus recovery cycle (1 ) 2 ? ns t lod laddr[18:2], ldata output disable to pdaen* low, bus recovery cycle (1 ) 4 ? ns t loe pdaen* high to laddr[18:2], ldata output enable, bus recovery cycle (1 ) 9 ? ns t mcs sysclk to mcs*[3:0] valid (1 ) 16ns t lav sysclk to laddr[1,0] valid (1, 2 ) 17ns t oel moe* active from sysclk (1, 3) 820ns t oeh moe* inactive from sysclk (1, 3) 110ns t wl mwr*, mwe[3:0] active from sysclk (1, 3) ? 16 ns t wh mwr*, mwe[3:0]* inactive to sysclk (1, 3) ? 1ns t be mwe[3:0]* byte enables valid from sysclk (rammode = 1) (1) 17ns t crd csr read data output valid 2 20 ns t cwds csr write data setup to sysclk 8 ? ns t cwdh csr write data hold from sysclk 0 ? ns t las laddr setup to sysclk 12 ? ns note(s): (1) see figures 16-13 and 16-14 for waveforms and definitions. (2) t lav is valid for second and subsequent accesses during burst transfers. see functional timing diagrams. (3) in the case of two cycle memory, or when inserting wait states by pwait*, moe*, mwe[3:0]*, and mwr* are extended across 2 or more clock cycles with the same relative timing to sysclk. see the functional timing diagrams in section 10.6 . cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.1 timing 28236-DSH-001-B mindspeed technologies ? 16-17 figure 16-13. local processor read timing t mcs t pdaenh t oeh t lod t loe t pdaenl t lav t crd (min) sysclk pwait* pdaen* laddr[18:2] laddr[1:0] ldata (ram read) ldata (csr or mcs[3:0]* moe* mwe[3:0]* mwr* prdy* lp addr t be mwe[3:0]* be t ov t crd (max) t oel t oh int. mem. read) t las 8236_088 16.0 electrical and mechanical specifications cn8236 16.1 timing atm servicesar plus with xbr traffic management 16-18 mindspeed technologies ? 28236-DSH-001-B figure 16-14. local processor write timing t mcs t pdaenh t wh t lod t pdaenl t lav t cwdh t loe lp data sysclk pwait* pdaen* laddr[18:2] laddr[1:0] ldata (csr or ldata (ram wr) mcs[3:0]* moe* mwe[3:0]* mwe[3:0]* be mwr* prdy* lp addr t wl t ov t oh int. mem. write) t las t cwds 8236_089 cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.2 absolute maximum ratings 28236-DSH-001-B mindspeed technologies ? 16-19 16.2 absolute maximum ratings stresses above those listed as absolute maximum ratings ( table 16-11 ) can cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in other sections of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device should be handled as an esd-sensitive device. voltage on any signal pin exceeding 5.5 v can induce destructive latchup. table 16-11. absolute maximum ratings parameter value unit supply voltage (vdd) ? 0.5 to +4 v input voltage ? 0.5 to +5.5 v output voltage ? 0.5 to (vdd + 0.3) v storage temperature ? 40 to 125 c maximum current @ max clock frequencies and 3.6 v 400 ma moisture sensitivity level (msl) 4 ? fit @ 55 c 55 ? theta ja (t a = 85 c, t j = 125 c) 17 c/w 16.0 electrical and mechanical specifications cn8236 16.3 dc characteristics atm servicesar plus with xbr traffic management 16-20 mindspeed technologies ? 28236-DSH-001-B 16.3 dc characteristics the dc electrical characteristics are listed in table 16-12 . table 16-12. dc characteristics (1 of 2) parameter conditions min max unit operating supply voltage (vdd) ? 3.0 3.6 v output voltage high i oh = ? 500 a (for all 3.3 v pci signaling) 0.9*vdd ? v i oh = ? 2 ma (for all 5 v pci signaling) 2.4 ? v i oh = 4.0 ma (for all other signals) 2.4 ? v output voltage low i ol = 1500 a (for all 3.3 v pci signals) ? 0.1*vdd v i oh = 3 ma, 6 ma (1) (for all 5 v pci signaling) ? 0.55 v i ol = 4.0 ma (for all other signals) ? 0.4 v input voltage high (pci) (for 3.3 v pci signaling) 0.5*vdd 5.25 v (for 5 v pci signaling) 2.0 5.25 v input voltage high (clk2x, rxclk, txclk) ? 0.7*vdd 5.25 v input voltage high (all others) ? 2.0 5.25 v input voltage low (pci) (for 3.3 v pci signaling) ? 0.5 0.3*vdd v (for 5 v pci signaling) ? 0.5 0.8 v input voltage low (clk2x, rxclk, txclk) ? 0 0.3*vdd v input voltage low (all others) ? 00.8v input leakage current vin = vdd or gnd ? 10 10 a cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.3 dc characteristics 28236-DSH-001-B mindspeed technologies ? 16-21 three-state output leakage current vout = vdd or gnd ? 10 10 a pullup current ? 30 100 a pulldown current ? 30 100 a input capacitance ?? 7pf output capacitance ?? 7pf note(s): all outputs are cmos drive levels, and can be used with cmos or ttl logic. (1) per pci specification rev 2.1, signals without pullup resistors must have 3 ma low output current. signals requiring pullup must have 6 ma. the latter include: frame*, trdy*, irdy*, devsel*, stop*, serr*, perr*, and lock*. table 16-12. dc characteristics (2 of 2) parameter conditions min max unit 16.0 electrical and mechanical specifications cn8236 16.4 mechanical specifications atm servicesar plus with xbr traffic management 16-22 mindspeed technologies ? 28236-DSH-001-B 16.4 mechanical specifications the cn8236 388-pin bga package is illustrated in figure 16-15 . figure 16-16 illustrates a pinout configuration of the cn8236, and pin listings are provided in tables 16-13 and 16-14 . cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.4 mechanical specifications 28236-DSH-001-B mindspeed technologies ? 16-23 figure 16-15. 388-pin ball grid array package (bga) 35.000 .100 30.000 ?.050 35.000 .100 30.000 ?.050 1.70 r typ 4 pl pin a1 triangle (underside) optional 45? chamfer typ 4 pl top view 15 ? 2.220 ?.220 before reflow 1.100 .050 .520 ?.070 seating plane .150 max 0.600 ?.100 before reflow side view 2.100 ref after reflow 0.480 ref after reflow 1.270 typ 15.875 31.750 bsc 31.750 bsc 1.270 typ 15.875 a 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af bottom view pin a1 triangle 0.75 ?0.15 dia notes: - all dimensions are in millimeters (mm). - reflow applies to soldering to host pc board. - ref: gp00-d353 - thermal balls in center connect to ground. 8236_090 16.0 electrical and mechanical specifications cn8236 16.4 mechanical specifications atm servicesar plus with xbr traffic management 16-24 mindspeed technologies ? 28236-DSH-001-B figure 16-16. cn8236 pinout configuration hfifowr0 hfifowr3 hfifowr1 hfifowr4 hfifowr5 hswitch_ hfifowr2 stat0 stat1 rammode mwe3_ mwe2_ mwe1_ mwe0_ moe_ mwr_ mcs3_ mcs2_ mcs1_ mcs0_ hled_ clkd3 sysclk clk2x ldata31 ldata30 ldata29 ldata28 ldata24 ldata25 ldata26 ldata27 ldata23 ldata21 ldata19 ldata18 ldata15 ldata14 ldata13 ldata12 ldata11 ldata10 ldata8 ldata7 ldata6 ldata5 ldata4 ldata2 ldata0 outvdd9 schref rxpar rxaddr1 rxaddr3 rxaddr2 rxaddr0 rxaddr4 rxd7 rxd6 rxd5 rxd13 rxd12 rxd11 rxd10 rxd15 rxd14 rxd9 rxd8 rxd2 rxd1 rxd0 rxsoc rxen_ txclk rxclav_ frcfg0 frcfg1 rxclk txen_ utopia1 txd15 txd11 txd12 txd13 txd14 txd8 txd9 txd10 txsoc txclav txpar txd7 txd6 txd5 txd4 txd3 txd2 txaddr4 txaddr0 txaddr1 txaddr2 txaddr3 txd1 txd0 tclk trst_ tdi hint_ hrst_ had30 had27 had25 hcbe3_ had23 had22 had17 hcbe2_ hclk hframe*_ hirdy*_ htrdy*_ hdevsel_ hstop_ hperr_ hserr_ hpar hcbe1_ had15 had14 had13 had12 had11 had10 had9 had8 had7 had6 had5 hcbe0_ had4 had3 had2 had1 had0 eepwr hfiford4 hfiford1 hfiford5 hfiford3 hfiford2 henum hfiford0 procmode prst_ pint_ pfail_ pdaen_ pcs_ pas_ pblast_ pwait_ prdy_ pwnr pbe_ pbe2_ pbe1_ pbe0_ pbsel1 pbsel0 paddr1 paddr0 laddr18 laddr17 laddr16 laddr15 laddr14 laddr13 laddr12 laddr11 laddr10 laddr9 laddr8 laddr7 laddr6 laddr5 laddr4 laddr3 laddr2 laddr1 laddr0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af scl spare-pme pci5v pvgg0 (viewed from top of device) ldata22 ldata20 ldata16 ldata17 ldata9 ldata3 ldata1 rxd4 rxd3 had16 had18 had19 had21 had20 hidsel had24 had26 had28 had29 had31 hreq_ hgnt_ sda tdo tms signal ground - vss power - vdd spare/no connect digital channel laddr12 8236_091a cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.4 mechanical specifications 28236-DSH-001-B mindspeed technologies ? 16-25 pin pin label i/o a1 gnd ? a2 vdd ? a3 laddr0 i/o a4 laddr3 i/o a5 laddr7 i/o a6 laddr9 i/o a7 laddr13 i/o a8 laddr15 i/o a9 vdd ? a10 pbsel0 i a11 gnd ? a12 vdd ? a13 pwait_ i a14 vdd ? a15 pcs_ i/o a16 prst_ o a17 spare ? a18 gnd ? a19 spare ? a20 spare ? a21 spare ? a22 spare ? a23 gnd ? a24 vdd ? a25 hfiford4 i a26 gnd ? b1 spare ? b2 vdd ? b3 gnd ? b4 laddr2 i/o b5 laddr6 i/o b6 laddr8 i/o b7 laddr12 i/o b8 laddr14 i/o b9 laddr18 i/o b10 paddr1 i b11 vdd ? b12 pbe3_ i b13 prdy_ o b14 gnd ? b15 pdaen_ i/o b16 procmode i b17 spare ? b18 spare ? b19 vdd ? b20 spare ? b21 spare ? b22 spare ? b23 henum_ od b24 gnd ? b25 vdd ? b26 hfiford1 i c1 gnd ? c2 hfifowr0 i c3 spare ? c4 laddr1 i/o c5 laddr5 i/o c6 gnd ? c7 laddr11 i/o c8 gnd ? c9 laddr17 i/o c10 paddr0 i c11 pbe0_ i c12 pbe2_ i c13 pwnr i/o c14 pblast_ i/o c15 pfail_ i c16 vdd ? c17 spare ? c18 spare ? pin pin label i/o c19 spare ? c20 gnd ? c21 spare ? c22 spare ? c23 hfiford5 i c24 hfiford2 i c25 hfiford0 i c26 gnd ? d1 hfifowr3 i d2 hfifowr2 i d3 hfifowr1 i d4 spare ? d5 laddr4 i/o d6 vdd ? d7 laddr10 i/o d8 vdd ? d9 laddr16 i/o d10 gnd ? d11 pbsel1 i d12 pbe1_ i d13 gnd ? d14 pas_ i/o d15 pint_ od d16 gnd ? d17 spare ? d18 spare ? d19 spare ? d20 spare ? d21 vdd ? d22 eepwr o d23 hfiford3 i d24 had0 i/o d25 had1 i/o d26 had2 i/o e1 vdd ? pin pin label i/o table 16-13. pin description (numeric list) (1 of 4) 16.0 electrical and mechanical specifications cn8236 16.4 mechanical specifications atm servicesar plus with xbr traffic management 16-26 mindspeed technologies ? 28236-DSH-001-B e2 gnd e3 hfifowr4 i e4 vgg i e23 had3 i/o e24 vdd ? e25 gnd ? e26 had4 i/o f1 stat0 o f2 stat1 o f3 hswitch_ i f4 hfifowr5 i f23 had5 i/o f24 had6 i/o f25 had7 i/o f26 hcbe0_ i/o g1 gnd g2 mwe2_ o g3 mwe3_ o g4 rammode i g23 vdd ? g24 gnd ? g25 had8 i/o g26 had9 i/o h1 moe_ o h2 mwe0_ o h3 mwe1_ o h4 vdd ? h23 had10 i/o h24 had11 i/o h25 had12 i/o h26 gnd ? j1 mcs2_ o j2 mcs3_ o j3 vdd ? j4 mwr_ o pin pin label i/o j23 vdd ? j24 had13 i/o j25 had14 i/o j26 had15 i/o k1 vdd ? k2 gnd ? k3 mcs0_ o k4 mcs1_ o k23 hcbe1_ i/o k24 hpar i/o k25 vdd ? k26 gnd ? l1 vdd ? l2 clkd3 o l3 vdd ? l4 hled_ od l23 hserr_ od l24 hperr_ i/o l25 hstop_ i/o l26 hdevsel_ i/o m1 gnd ? m2 sysclk o m3 gnd ? m4 spare ? m23 htrdy_ i/o m24 hirdy_ i/o m25 hframe_ i/o m26 gnd n1 ldata31 i/o n2 gnd ? n3 vdd ? n4 clk2x i n23 hclk i n24 vdd ? n25 gnd ? pin pin label i/o n26 hcbe2_ i/o p1 ldata30 i/o p2 ldata29 i/o p3 ldata28 i/o p4 vdd ? p23 gnd ? p24 had18 i/o p25 had17 i/o p26 had16 i/o r1 ldata27 i/o r2 ldata26 i/o r3 ldata25 i/o r4 ldata24 i/o r23 had22 i/o r24 had21 i/o r25 had20 i/o r26 had19 i/o t1 gnd ? t2 vdd ? t3 ldata23 i/o t4 ldata22 i/o t23 hcbe3_ i/o t24 hidsel i t25 had23 i/o t26 vdd ? u1 ldata21 i/o u2 vdd ? u3 ldata20 i/o u4 ldata19 i/o u23 had25 i/o u24 had24 i/o u25 gnd ? u26 vdd ? v1 ldata18 i/o v2 gnd ? pin pin label i/o table 16-13. pin description (numeric list) (2 of 4) cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.4 mechanical specifications 28236-DSH-001-B mindspeed technologies ? 16-27 v3 ldata17 i/o v4 ldata16 i/o v23 vdd ? v24 had28 i/o v25 had27 i/o v26 had26 i/o w1 ldata15 i/o w2 ldata14 i/o w3 ldata13 i/o w4 gnd ? w23 gnd ? w24 had31 i/o w25 had30 i/o w26 had29 i/o y1 ldata12 i/o y2 ldata11 i/o y3 ldata10 i/o y4 ldata9 i/o y23 hrst_ i y24 gnd ? y25 hgnt_ i y26 hreq_ o aa1 ldata8 i/o aa2 gnd ? aa3 ldata7 i/o aa4 ldata6 i/o aa23 gnd ? aa24 vdd ? aa25 hint_ od aa26 vdd ? ab1 ldata5 i/o ab2 ldata4 i/o ab3 vdd ? ab4 ldata3 i/o ab23 scl o pin pin label i/o ab24 sda i/o ab25 spare ? ab26 pci5v i ac1 ldata2 i/o ac2 ldata1 i/o ac3 ldata0 i/o ac4 gnd ? ac5 vdd ? ac6 rxd13 i ac7 rxd9 i ac8 rxd5 i ac9 rxd1 i ac10 rxsoc i ac11 spare ? ac12 vdd ? ac13 rxclk i ac14 txen_ i/o ac15 spare ? ac16 txd15 o ac17 txd11 o ac18 txd8 o ac19 vdd ? ac20 txd2 o ac21 txaddr4 i/o ac22 txaddr0 i/o ac23 tclk i ac24 tdo o ac25 tdi i ac26 vdd ? ad1 gnd ? ad2 vdd ? ad3 spare ? ad4 rxaddr1 i/o ad5 rxpar i ad6 rxd12 i pin pin label i/o ad7 rxd8 i ad8 rxd4 i ad9 gnd ? ad10 rxen_ i/o ad11 spare ? ad12 txclk i ad13 gnd ? ad14 utopia1 i ad15 spare ? ad16 vdd ? ad17 txd12 o ad18 txd9 o ad19 gnd ? ad20 txd3 o ad21 vdd ? ad22 txaddr1 i/o ad23 spare ? ad24 spare ? ad25 trst_ i ad26 tms i ae1 schref i ae2 vdd ? ae3 rxaddr3 i/o ae4 rxaddr0 i/o ae5 rxd15 i ae6 rxd11 i ae7 rxd7 i ae8 rxd3 i ae9 vdd ? ae10 gnd ? ae11 rxclav i/o ae12 frcfg0 i ae13 vdd ? ae14 vdd ? ae15 spare ? pin pin label i/o table 16-13. pin description (numeric list) (3 of 4) 16.0 electrical and mechanical specifications cn8236 16.4 mechanical specifications atm servicesar plus with xbr traffic management 16-28 mindspeed technologies ? 28236-DSH-001-B ae16 txpar o ae17 txd13 o ae18 txd10 o ae19 txd6 o ae20 txd4 o ae21 txd0 o ae22 txaddr2 i/o ae23 vdd ? ae24 spare ? ae25 vdd ? ae26 vdd ? af1 gnd ? af2 rxaddr4 i/o pin pin label i/o af3 rxaddr2 i/o af4 gnd ? af5 rxd14 i af6 rxd10 i af7 rxd6 i af8 rxd2 i af9 rxd0 i af10 spare ? af11 spare ? af12 frcfg1 i af13 spare ? af14 gnd ? af15 txsoc i/o pin pin label i/o af16 txclav_ i/o af17 txd14 o af18 gnd ? af19 txd7 o af20 txd5 o af21 txd1 o af22 txaddr3 i/o af23 gnd ? af24 vdd ? af25 spare ? af26 gnd ? pin pin label i/o table 16-13. pin description (numeric list) (4 of 4) cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.4 mechanical specifications 28236-DSH-001-B mindspeed technologies ? 16-29 pin label pin i/o clk2x n4 i clkd3 l2 o eepwr d22 o frcfg0 ae12 i frcfg1 af12 i rxclk ac13 i gnd a1 ? gnd a11 ? gnd a18 ? gnd a23 ? gnd a26 ? gnd b3 ? gnd b14 ? gnd b24 ? gnd c1 ? gnd c6 ? gnd c8 ? gnd c20 ? gnd c26 ? gnd d10 ? gnd d13 ? gnd d16 ? gnd e2 ? gnd e25 ? gnd g1 ? gnd g24 ? gnd h26 ? gnd k2 ? gnd k26 ? gnd m1 ? gnd m3 ? gnd m26 ? gnd n2 ? gnd n25 ? gnd p23 ? gnd t1 ? gnd u25 ? gnd v2 ? gnd w23 ? gnd w4 ? gnd y24 ? gnd aa2 ? gnd aa23 ? gnd ac4 ? gnd ad1 ? gnd ad13 ? gnd ad19 ? gnd ad9 ? gnd ae10 ? gnd af1 ? gnd af4 ? gnd af14 ? gnd af18 ? gnd af23 ? gnd af26 ? had0 d24 i/o had1 d25 i/o had2 d26 i/o had3 e23 i/o had4 e26 i/o had5 f23 i/o had6 f24 i/o had7 f25 i/o had8 g25 i/o had9 g26 i/o had10 h23 i/o had11 h24 i/o had12 h25 i/o had13 j24 i/o had14 j25 i/o pin label pin i/o had15 j26 i/o had16 p26 i/o had17 p25 i/o had18 p24 i/o had19 r26 i/o had20 r25 i/o had21 r24 i/o had22 r23 i/o had23 t25 i/o had24 u24 i/o had25 u23 i/o had26 v26 i/o had27 v25 i/o had28 v24 i/o had29 w26 i/o had30 w25 i/o had31 w24 i/o hcbe0_ f26 i/o hcbe1_ k23 i/o hcbe2_ n26 i/o hcbe3_ t23 i/o hclk n23 i hdevsel_ l26 i/o henum_ b23 od hfiford0 c25 i hfiford1 b26 i hfiford2 c24 i hfiford3 d23 i hfiford4 a25 i hfiford5 c23 i hfifowr0 c2 i hfifowr1 d3 i hfifowr2 d2 i hfifowr3 d1 i hfifowr4 e3 i pin label pin i/o table 16-14. pin description (alphabetic list) (1 of 4) 16.0 electrical and mechanical specifications cn8236 16.4 mechanical specifications atm servicesar plus with xbr traffic management 16-30 mindspeed technologies ? 28236-DSH-001-B hfifowr5 f4 i hframe_ m25 i/o hgnt_ y25 i hidsel t24 i hint_ aa25 od hirdy_ m24 i/o hled_ l4 od hpar k24 i/o hperr_ l24 i/o hreq_ y26 o hrst_ y23 i hserr_ l23 od hstop_ l25 i/o hswitch_ f3 i htrdy_ m23 i/o laddr0 a3 i/o laddr1 c4 i/o laddr2 b4 i/o laddr3 a4 i/o laddr4 d5 i/o laddr5 c5 i/o laddr6 b5 i/o laddr7 a5 i/o laddr8 b6 i/o laddr9 a6 i/o laddr10 d7 i/o laddr11 c7 i/o laddr12 b7 i/o laddr13 a7 i/o laddr14 b8 i/o laddr15 a8 i/o laddr16 d9 i/o laddr17 c9 i/o laddr18 b9 i/o ldata0 ac3 i/o pin label pin i/o ldata1 ac2 i/o ldata2 ac1 i/o ldata3 ab4 i/o ldata4 ab2 i/o ldata5 ab1 i/o ldata6 aa4 i/o ldata7 aa3 i/o ldata8 aa1 i/o ldata9 y4 i/o ldata10 y3 i/o ldata11 y2 i/o ldata12 y1 i/o ldata13 w3 i/o ldata14 w2 i/o ldata15 w1 i/o ldata16 v4 i/o ldata17 v3 i/o ldata18 v1 i/o ldata19 u4 i/o ldata20 u3 i/o ldata21 u1 i/o ldata22 t4 i/o ldata23 t3 i/o ldata24 r4 i/o ldata25 r3 i/o ldata26 r2 i/o ldata27 r1 i/o ldata28 p3 i/o ldata29 p2 i/o ldata30 p1 i/o ldata31 n1 i/o mcs0_ k3 o mcs1_ k4 o mcs2_ j1 o mcs3_ j2 o pin label pin i/o moe_ h1 o mwe0_ h2 o mwe1_ h3 o mwe2_ g2 o mwe3_ g3 o mwr_ j4 o paddr0 c10 i paddr1 b10 i pas_ d14 i/o pbe0_ c11 i pbe1_ d12 i pbe2_ c12 i pbe3_ b12 i pblast_ c14 i/o pbsel0 a10 i pbsel1 d11 i pci5v ab26 i pcs_ a15 i/o pdaen_ b15 i/o pfail_ c15 i pint_ d15 od prdy_ b13 o procmode b16 i prst_ a16 o pwait_ a13 i pwnr c13 i/o rammode g4 i rxaddr0 ae4 i/o rxaddr1 ad4 i/o rxaddr2 af3 i/o rxaddr3 ae3 i/o rxaddr4 af2 i/o rxd0 af9 i rxd1 ac9 i rxd2 af8 i pin label pin i/o table 16-14. pin description (alphabetic list) (2 of 4) cn8236 16.0 electrical and mechanical specifications atm servicesar plus with xbr traffic management 16.4 mechanical specifications 28236-DSH-001-B mindspeed technologies ? 16-31 rxd3 ae8 i rxd4 ad8 i rxd5 ac8 i rxd6 af7 i rxd7 ae7 i rxd8 ad7 i rxd9 ac7 i rxd10 af6 i rxd11 ae6 i rxd12 ad6 i rxd13 ac6 i rxd14 af5 i rxd15 ae5 i rxen_ ad10 i/o rxclav ae11 i/o rxsoc ac10 i rxpar ad5 i schref ae1 i scl ab23 o sda ab24 i/o spare a17 ? spare a19 ? spare a20 ? spare a21 ? spare a22 ? spare b1 ? spare b17 ? spare b18 ? spare b20 ? spare b21 ? spare b22 ? spare c3 ? spare c17 ? spare c18 ? spare c19 ? pin label pin i/o spare c21 ? spare c22 ? spare d4 ? spare d17 ? spare d18 ? spare d19 ? spare d20 ? spare m4 ? spare ab25 ? spare ac11 ? spare ac15 ? spare ad11 ? spare ad15 ? spare ad23 ? spare ad24 ? spare ad3 ? spare ae15 ? spare ae24 ? spare af10 ? spare af11 ? spare af13 ? spare af25 ? stat0 f1 o stat1 f2 o sysclk m2 o tclk ac23 i tdi ac25 i tdo ac24 o tms ad26 i trst_ ad25 i txaddr0 ac22 i/o txaddr1 ad22 i/o txaddr2 ae22 i/o txaddr3 af22 i/o txaddr4 ac21 i/o pin label pin i/o txclk ad12 i txd0 ae21 o txd1 af21 o txd2 ac20 o txd3 ad20 o txd4 ae20 o txd5 af20 o txd6 ae19 o txd7 af19 o txd8 ac18 o txd9 ad18 o txd10 ae18 o txd11 ac17 o txd12 ad17 o txd13 ae17 o txd14 af17 o txd15 ac16 o txen_ ac14 i txclav_ af16 i/o txsoc af15 i/o txpar ae16 o utopia1 ad14 i vdd a2 ? vdd a9 ? vdd a12 ? vdd a14 ? vdd a24 ? vdd b2 ? vdd b11 ? vdd b19 ? vdd b25 ? vdd c16 ? vdd d21 ? vdd d6 ? vdd d8 ? pin label pin i/o table 16-14. pin description (alphabetic list) (3 of 4) 16.0 electrical and mechanical specifications cn8236 16.4 mechanical specifications atm servicesar plus with xbr traffic management 16-32 mindspeed technologies ? 28236-DSH-001-B vdd e1 ? vdd e24 ? vdd g23 ? vdd h4 ? vdd j3 ? vdd j23 ? vdd k1 ? vdd k25 ? vdd l1 ? vdd l3 ? vdd n24 ? vdd n3 ? vdd p4 ? vdd t2 ? pin label pin i/o vdd t26 ? vdd u2 ? vdd u26 ? vdd v23 ? vdd aa24 ? vdd aa26 ? vdd ab3 ? vdd ac5 ? vdd ac12 ? vdd ac19 ? vdd ac26 ? vdd ad2 ? vdd ad16 ? vdd ad21 ? pin label pin i/o vdd ae2 ? vdd ae9 ? vdd ae13 ? vdd ae14 ? vdd ae23 ? vdd ae25 ? vdd ae26 ? vdd af24 ? vgg e4 i pin label pin i/o table 16-14. pin description (alphabetic list) (4 of 4) the pins listed in table 16-15 have been selected as future inputs. when designing the printed circuit board, tie these pins to ground for backward compatibility of future parts. table 16-15. spare pins reserved for inputs pin comments af11 tied to ground on pcb for forward compatibility. af13 tied to ground on pcb for forward compatibility. ad23 tied to ground on pcb for forward compatibility. ae24 tied to ground on pcb for forward compatibility. 28236-DSH-001-B mindspeed technologies ? a-1 a appendix a: boundary scan the cn8236 supports boundary scan testing conforming to ieee standard 1149.1-1990 and supplement b , 1994. this appendix is intended to assist the customer in developing boundary scan tests for printed circuit boards and systems that use the cn8236. it is assumed that the reader is familiar with boundary scan terminology. the boundary scan section of the cn8236 provides access to all external i/o signals of the device for board and system-level testing. this circuitry also conforms to ieee std 1149.1-1990. the boundary scan test logic is accessed through five dedicated pins on the cn8236 (see table a-1 ). table a-1. boundary scan signals pin name signal name i/o definition trst* test logic reset in when at a logic low, this signal asynchronously resets the boundary scan test circuitry and puts the test controller into the reset state. this state allows normal system operation. tclk test clock in test clocking is generated externally by the system board or by the tester. tclk can be stopped in either the high state or the low state. tms test mode select in decoded to control test operations. tdo serial test data output out outputs serial test pattern data. tdi serial test data input in input for serial test pattern data. appendix a: boundary scan cn8236 atm servicesar plus with xbr traffic management a-2 mindspeed technologies ? 28236-DSH-001-B the test circuitry includes the boundary scan register, a bypass register, an instruction register (ir), and the tap access port (tap) controller (see figure a-1 ). figure a-1. test circuitry block diagram 363-bit boundary scan register 362 1-bit bypass register 3-bit instruction register tap controller 30 tms tclk trst* tdi mux tdo 0 8236_092 note(s): if the boundary scan circuitry of the cn8237 is not being used, tie tclk and trst* to ground. cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.1 instruction register 28236-DSH-001-B mindspeed technologies ? a-3 a.1 instruction register the instruction register is a 4-bit register with no parity. when the boundary scan circuitry is reset, the ir is loaded with the binary value b1111, which is equivalent to the bypass instruction value. the capture-ir binary value is b0001, and is shifted out tdo as the ir is loaded. the sixteen instructions include three ieee 1149.1 mandatory public instructions (bypass, extest, and sample/preload) and thirteen private instructions for manufacturing use only. bit-0 (lsb) is shifted into the instruction register first. table a-2 shows the bit settings for this register. note: the implementation of this register as described is applicable only to rev. a of cn8236 device. table a-2. ieee std. 1149.1 instructions bit 3 bit 2 bit 1 bit 0 instruction register accessed 0 0 0 0 extest boundary scan 0 0 0 1 rsthigh - private ? 0 0 1 0 sample/preload boundary scan 0011tmwafifo - private ? 0 1 0 0 tmwbfifo - private ? 0101tmrfifo - private ? 0 1 1 0 tsegfifo - private ? 0 1 1 1 trsmfifo - private ? 1 0 0 0 t38afifo - private ? 1 0 0 1 t38vbfifo - private ? 1010rsvd0 - private ? 1011rsvd1 - private ? 1 1 0 0 rsvd2 - private boundary scan 1 1 0 1 rsvd3 - private boundary scan 1110pm_en - private ? 1111bypass ? appendix a: boundary scan cn8236 a.2 bypass register atm servicesar plus with xbr traffic management a-4 mindspeed technologies ? 28236-DSH-001-B a.2 bypass register the bypass register is a 1-bit shift register used to pass tdi data to tdo to facilitate the testing of other devices in the scan path without having to shift the data patterns through the complete boundary scan register of the cn8236. a.3 boundary scan register the boundary scan register consists of two different types of registers corresponding to ieee std. 1149.1a-1993 attributes and definitions. these register names are std_1149_1_1993 standard boundary cell names bc-1, and bc-7. cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.4 boundary scan register cells 28236-DSH-001-B mindspeed technologies ? a-5 a.4 boundary scan register cells table a-3 defines the boundary scan register cells. cell 0 is closest to tdo in the chain. these are the cell type definitions: output3 = output-tri-state input = input-observe bidir = reversible cell for bidirectional pin control = output-control controlr = output-control that is forced to its disable state in the test-logic-reset controller state. internal = control-and-observe internal cell, not associated with an i/o pin. all controlling cells put their respective output cell into the inactive state with a value of 1. table a-3. boundary scan register cells (1 of 8) cell related pin name cell type controlling cell 0 stat[1] output3 30 1 laddr[0] output3 30 2 laddr[1] output3 30 3 laddr[2] bidir 19 4 laddr[3] bidir 19 5 laddr[4] bidir 19 6 laddr[5] bidir 19 7 laddr[6] bidir 19 8 laddr[7] bidir 19 9 laddr[8] bidir 19 10 laddr[9] bidir 19 11 laddr[10] bidir 19 12 laddr[11] bidir 19 13 laddr[12] bidir 19 14 laddr[13] bidir 19 15 laddr[14] bidir 19 16 laddr[15] bidir 19 17 laddr[16] bidir 19 18 laddr[17] bidir 19 19 ? control ? appendix a: boundary scan cn8236 a.4 boundary scan register cells atm servicesar plus with xbr traffic management a-6 mindspeed technologies ? 28236-DSH-001-B 20 laddr[18] bidir 19 21 paddr[0] input ? 22 paddr[1] input ? 23 pbsel[0] input ? 24 pbsel[1] input ? 25 pbe[0]_neg input ? 26 pbe[1]_neg input ? 27 pbe[2]_neg input ? 28 pbe[3]_neg input ? 29 pwnr bidir 35 30 ? control ? 31 prdy_neg output3 30 32 pwait_neg input ? 33 pblast_neg bidir 35 34 pas_neg bidir 35 35 ? control ? 36 pcs_neg bidir 35 37 ? control ? 38 pdaen_neg bidir 37 39 pfail_neg input ? 40 ? control ? 41 pint_neg output3 40 42 prst_neg output3 30 43 procmode input ? 44 had[0] bidir 60 45 had[1] bidir 60 46 had[2] bidir 60 47 had[3] bidir 60 48 had[4] bidir 60 49 had[5] bidir 60 50 eepwr output3 30 51 ? control ? 52 henum_neg output3 51 53 hfiford[5] input ? table a-3. boundary scan register cells (2 of 8) cell related pin name cell type controlling cell cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.4 boundary scan register cells 28236-DSH-001-B mindspeed technologies ? a-7 54 hfiford[4] input ? 55 hfiford[3] input ? 56 hfiford[2] input ? 57 hfiford[1] input ? 58 hfiford[0] input ? 59 had[6] bidir 60 60 ? control ? 61 had[7] bidir 60 62 hcbe[0]_neg bidir 102 63 had[8] bidir 70 64 had[9] bidir 70 65 had[10] bidir 70 66 had[11] bidir 70 67 had[12] bidir 70 68 had[13] bidir 70 69 had[14] bidir 70 70 ? control ? 71 had[15] bidir 70 72 hcbe[1]_neg bidir 102 73 ? control ? 74 hpar bidir 73 75 ? control ? 76 hserr_neg bidir 75 77 ? control ? 78 hperr_neg bidir 77 79 ? control ? 80 hstop_neg bidir 79 81 ? control ? 82 hdevsel_neg bidir 81 83 ? control ? 84 htrdy_neg bidir 83 85 ? control ? 86 hirdy_neg bidir 85 87 ? control ? table a-3. boundary scan register cells (3 of 8) cell related pin name cell type controlling cell appendix a: boundary scan cn8236 a.4 boundary scan register cells atm servicesar plus with xbr traffic management a-8 mindspeed technologies ? 28236-DSH-001-B 88 hframe_neg bidir 87 89 hclk input ? 90 ? internal ? 91 hcbe[2]_neg bidir 102 92 had[16] bidir 99 93 had[17] bidir 99 94 had[18] bidir 99 95 had[19] bidir 99 96 had[20] bidir 99 97 had[21] bidir 99 98 had[22] bidir 99 99 ? control ? 100 had[23] bidir 99 101 hidsel input ? 102 ? control ? 103 hcbe[3]_neg bidir 102 104 had[24] bidir 111 105 had[25] bidir 111 106 had[26] bidir 111 107 had[27] bidir 111 108 had[28] bidir 111 109 had[29] bidir 111 110 had30 bidir 111 111 ? control ? 112 had[31] bidir 111 113 ? control ? 114 hreq_neg bidir 113 115 hgnt_neg input ? 116 hrst_neg input ? 117 txdata[8] output3 145 118 txdata[9] output3 145 119 txdata]10[ output3 145 120 txdata[11] output3 145 121 txdata[12] output3 145 table a-3. boundary scan register cells (4 of 8) cell related pin name cell type controlling cell cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.4 boundary scan register cells 28236-DSH-001-B mindspeed technologies ? a-9 122 txdata[13] output3 145 123 txdata[14] output3 145 124 txdata[15] output3 145 125 ? control ? 126 hint_neg bidir 125 127 pci5v input ? 128 ? control ? 129 sda bidir 128 130 ? control ? 131 scl bidir 130 132 txaddr[0] bidir 136 133 txaddr[1] bidir 136 134 txaddr[2] bidir 136 135 txaddr[3] bidir 136 136 ? control ? 137 txaddr[4] bidir 136 138 txdata[0] output3 145 139 txdata[1] output3 145 140 txdata[2] output3 145 141 txdata[3] output3 145 142 txdata[4] output3 145 143 txdata[5] output3 145 144 txdata[6] output3 145 145 ? control ? 146 txdata[7] output3 145 147 txpar output3 145 148 ? control ? 149 txclav_neg bidir 148 150 ? control ? 151 txsoc output3 150 152 ? control ? 153 txen_neg bidir 152 154 utopia[1] input ? 155 frctrl input ? table a-3. boundary scan register cells (5 of 8) cell related pin name cell type controlling cell appendix a: boundary scan cn8236 a.4 boundary scan register cells atm servicesar plus with xbr traffic management a-10 mindspeed technologies ? 28236-DSH-001-B 156 frcfg[1] input ? 157 frcfg[0] input ? 158 txclk input ? 159 ? control ? 160 rxclav_neg bidir 159 161 ? control ? 162 rxen_neg bidir 161 163 rxsoc input ? 164 rxdata[0] input ? 165 rxdata[1] input ? 166 rxdata[2] input ? 167 rxdata[3] input ? 168 rxdata[4] input ? 169 rxdata[5] input ? 170 rxdata[6] input ? 171 rxdata[7] input ? 172 rxpar input ? 173 rxaddr[0] bidir 177 174 rxaddr[1] bidir 177 175 rxaddr[2] bidir 177 176 rxaddr[3] bidir 177 177 ? control ? 178 rxaddr[4] bidir 177 179 schref input ? 180 ldata[0] bidir 195 181 ldata[1] bidir 195 182 ldata[2] bidir 195 183 ldata[3] bidir 195 184 rxdata[8] input ? 185 rxdata[9] input ? 186 rxdata[10] input ? 187 rxdata[11] input ? 188 rxdata[12] input ? 189 rxdata[13] input ? table a-3. boundary scan register cells (6 of 8) cell related pin name cell type controlling cell cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.4 boundary scan register cells 28236-DSH-001-B mindspeed technologies ? a-11 190 rxdata[14] input ? 191 rxdata[15] input ? 192 ldata[4] bidir 195 193 ldata[5] bidir 195 194 ldata[6] bidir 195 195 ? control ? 196 ldata[7] bidir 195 197 ldata[8] bidir 204 198 ldata[9] bidir 204 199 ldata[10] bidir 204 200 ldata[11] bidir 204 201 ldata[12] bidir 204 202 ldata[13] bidir 204 203 ldata[14] bidir 204 204 ? control ? 205 ldata[15] bidir 204 206 ldata[16] bidir 213 207 ldata[17] bidir 213 208 ldata[18] bidir 213 209 ldata[19] bidir 213 210 ldata[20] bidir 213 211 ldata[21] bidir 213 212 ldata[22] bidir 213 213 ? control ? 214 ldata[23] bidir 213 215 ldata[24] bidir 222 216 ldata[25] bidir 222 217 ldata[26] bidir 222 218 ldata[27] bidir 222 219 ldata[28] bidir 222 220 ldata[29] bidir 222 221 ldata[30] bidir 222 222 ? control ? 223 ldata[31] bidir 222 table a-3. boundary scan register cells (7 of 8) cell related pin name cell type controlling cell appendix a: boundary scan cn8236 a.4 boundary scan register cells atm servicesar plus with xbr traffic management a-12 mindspeed technologies ? 28236-DSH-001-B 224 clk2x input ? 225 sysclk output3 30 226 ? internal ? 227 clkd3 output3 30 228 ? control ? 229 hled_neg output3 228 230 mcs[0]_neg output3 30 231 mcs[1]_neg output3 30 232 mcs[2]_neg output3 30 233 mcs[3]_neg output3 30 234 mwr_neg output3 30 235 moe_neg output3 30 236 mwe[0]_neg output3 30 237 mwe[1]_neg output3 30 238 mwe[2]_neg output3 30 239 mwe[3]_neg output3 30 240 rammode input ? 241 stat[0] output3 30 242 hswitch_neg input ? 243 hfifowr[5] input ? 244 hfifowr[4] input ? 245 hfifowr[3] input ? 246 hfifowr[2] input ? 247 hfifowr[1] input ? 248 hfifowr[0] input ? table a-3. boundary scan register cells (8 of 8) cell related pin name cell type controlling cell cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.5 electrical characteristics 28236-DSH-001-B mindspeed technologies ? a-13 a.5 electrical characteristics this section describes the electrical characteristics for boundary scan. table a-4 provides timing specifications and figure a-2 shows a timing diagram. table a-4. timing specifications symbol description min max unit ? tclk frequency ? 20 mhz t cyc tclk cycle 50 ? ns t high tclk high pulse width 20 30 ns t low tclk low pulse width 20 30 ns t rise tclk rise 1 4 ns t fall tclk fall 1 4 ns t sur trst* inactive to tclk rising edge (1) 5 ? ns t hr trst* inactive after tclk rising edge (1) 5 ? ns t rst trst* active 1 ? t cyc t su tdi, tms, and data inputs setup 5 ? ns t h tdi, tms, and data inputs hold 5 ? ns t out tdo and data outputs valid ? 10 ns t on tdo and data outputs float to valid ? 10 ns t off tdo and data outputs valid to float ? 10 ns note(s): (1) trst* going inactive timing only required if tms = 0 at the rising edge of tclk. appendix a: boundary scan cn8236 a.5 electrical characteristics atm servicesar plus with xbr traffic management a-14 mindspeed technologies ? 28236-DSH-001-B figure a-2. timing diagram t rise t fall 1.5 t high t low t rst t sur t cyc t su t h t out data valid data valid t on data valid t off t hr data outputs, tdo data inputs, tdi,tms data outputs, tdo data outputs, tdo tclk trst* 8236_093 cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-15 a.6 boundary scan description language (bsdl) file to obtain an electronic copy of this file, go to the mindspeed web site at www.mindspeed.com. --------------------------------------------------------------------------- -- boundary scan description language (ieee 1149.1b) -- bsdl for device cn8236 -- bsdl file created by ? topgen ? revision 2.1 -- (c) mindspeed, inc. --------------------------------------------------------------------------- entity cn8236 is generic (physical_pin_map : string := "bga_352"); port ( hfifowr0 : in bit; hfifowr1 : in bit; hfifowr2 : in bit; hfifowr3 : in bit; hfifowr4 : in bit; hfifowr5 : in bit; hswitch_neg : in bit; stat0 : out bit; rammode : in bit; mwe3_neg : out bit; mwe2_neg : out bit; outgnd0 : linkage bit; outvdd0 : linkage bit; mwe1_neg : out bit; mwe0_neg : out bit; moe_neg : out bit; mwr_neg : out bit; outvdd1 : linkage bit; mcs3_neg : out bit; mcs2_neg : out bit; mcs1_neg : out bit; mcs0_neg : out bit; outgnd1 : linkage bit; outvdd2 : linkage bit; hled_neg : out bit; outvdd3 : linkage bit; clkd3 : out bit; outvdd4 : linkage bit; outgnd2 : linkage bit; sysclk : out bit; appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-16 mindspeed technologies ? 28236-DSH-001-B outgnd3 : linkage bit; clk2x : in bit; outvdd5 : linkage bit; outgnd4 : linkage bit; ldata31 : inout bit; ldata30 : inout bit; ldata29 : inout bit; ldata28 : inout bit; outvdd6 : linkage bit; ldata27 : inout bit; ldata26 : inout bit; ldata25 : inout bit; ldata24 : inout bit; outgnd5 : linkage bit; outvdd7 : linkage bit; ldata23 : inout bit; ldata22 : inout bit; ldata21 : inout bit; outvdd8 : linkage bit; ldata20 : inout bit; ldata19 : inout bit; ldata18 : inout bit; outgnd6 : linkage bit; ldata17 : inout bit; ldata16 : inout bit; ldata15 : inout bit; ldata14 : inout bit; ldata13 : inout bit; outgnd7 : linkage bit; ldata12 : inout bit; ldata11 : inout bit; ldata10 : inout bit; ldata9 : inout bit; ldata8 : inout bit; outgnd8 : linkage bit; ldata7 : inout bit; ldata6 : inout bit; ldata5 : inout bit; ldata4 : inout bit; outvdd9 : linkage bit; rxdata15 : in bit; rxdata14 : in bit; rxdata13 : in bit; rxdata12 : in bit; rxdata11 : in bit; rxdata10 : in bit; rxdata9 : in bit; rxdata8 : in bit; cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-17 ldata3 : inout bit; ldata2 : inout bit; ldata1 : inout bit; ldata0 : inout bit; outgnd9 : linkage bit; outvdd10 : linkage bit; schref : in bit; cgnd0 : linkage bit; cvdd0 : linkage bit; outgnd10 : linkage bit; rxaddr4 : inout bit; rxaddr3 : inout bit; rxaddr2 : inout bit; rxaddr1 : inout bit; rxaddr0 : inout bit; outgnd11 : linkage bit; outvdd11 : linkage bit; rxpar : in bit; rxdata7 : in bit; rxdata6 : in bit; rxdata5 : in bit; rxdata4 : in bit; rxdata3 : in bit; rxdata2 : in bit; rxdata1 : in bit; outgnd12 : linkage bit; outvdd12 : linkage bit; rxdata0 : in bit; rxsoc : in bit; rxen_neg : inout bit; outgnd13 : linkage bit; rxclav_neg : inout bit; outvdd13 : linkage bit; txclk : in bit; frcfg0 : in bit; frcfg1 : in bit; frctrl : in bit; outgnd14 : linkage bit; outvdd14 : linkage bit; outgnd15 : linkage bit; outvdd15 : linkage bit; utopia1 : in bit; txen_neg : inout bit; txsoc : out bit; txclav_neg : inout bit; txpar : out bit; txdata7 : out bit; txdata6 : out bit; appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-18 mindspeed technologies ? 28236-DSH-001-B outgnd16 : linkage bit; outvdd16 : linkage bit; txdata5 : out bit; txdata4 : out bit; txdata3 : out bit; txdata2 : out bit; txdata1 : out bit; txdata0 : out bit; outvdd17 : linkage bit; txaddr4 : inout bit; txaddr3 : inout bit; txaddr2 : inout bit; txaddr1 : inout bit; txaddr0 : inout bit; outgnd17 : linkage bit; outvdd18 : linkage bit; outvdd19 : linkage bit; cgnd1 : linkage bit; cvdd1 : linkage bit; tclk : in bit; outvdd20 : linkage bit; trst_neg : in bit; tms : in bit; tdo : out bit; tdi : in bit; outvdd21 : linkage bit; scl : inout bit; sda : inout bit; pci5v : in bit; outgnd18 : linkage bit; outvdd22 : linkage bit; hint_neg : inout bit; outvdd23 : linkage bit; txdata15 : out bit; txdata14 : out bit; txdata13 : out bit; txdata12 : out bit; txdata11 : out bit; outgnd19 : linkage bit; txdata10 : out bit; txdata9 : out bit; txdata8 : out bit; outvdd24 : linkage bit; hrst_neg : inout bit; outgnd20 : linkage bit; hgnt_neg : inout bit; hreq_neg : inout bit; outgnd21 : linkage bit; cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-19 had31 : inout bit; had30 : inout bit; had29 : inout bit; outvdd25 : linkage bit; had28 : inout bit; had27 : inout bit; had26 : inout bit; had25 : inout bit; had24 : inout bit; outgnd22 : linkage bit; outvdd26 : linkage bit; hcbe3_neg : inout bit; hidsel : inout bit; had23 : inout bit; outvdd27 : linkage bit; had22 : inout bit; had21 : inout bit; had20 : inout bit; had19 : inout bit; outgnd23 : linkage bit; had18 : inout bit; had17 : inout bit; had16 : inout bit; hcbe2_neg : inout bit; outgnd24 : linkage bit; outvdd28 : linkage bit; hclk : inout bit; outgnd25 : linkage bit; hframe_neg : inout bit; hirdy_neg : inout bit; htrdy_neg : inout bit; hdevsel_neg : inout bit; hstop_neg : inout bit; hperr_neg : inout bit; hserr_neg : inout bit; outgnd26 : linkage bit; outvdd29 : linkage bit; hpar : inout bit; hcbe1_neg : inout bit; had15 : inout bit; had14 : inout bit; had13 : inout bit; outvdd30 : linkage bit; outgnd27 : linkage bit; had12 : inout bit; had11 : inout bit; had10 : inout bit; had9 : inout bit; appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-20 mindspeed technologies ? 28236-DSH-001-B had8 : inout bit; outgnd28 : linkage bit; outvdd31 : linkage bit; hcbe0_neg : inout bit; had7 : inout bit; had6 : inout bit; hfiford0 : in bit; hfiford1 : in bit; hfiford2 : in bit; hfiford3 : in bit; hfiford4 : in bit; hfiford5 : in bit; henum_neg : out bit; eepwr : out bit; had5 : inout bit; had4 : inout bit; outgnd29 : linkage bit; outvdd32 : linkage bit; had3 : inout bit; had2 : inout bit; had1 : inout bit; had0 : inout bit; outgnd30 : linkage bit; outgnd31 : linkage bit; outvdd33 : linkage bit; outgnd32 : linkage bit; outvdd34 : linkage bit; outgnd33 : linkage bit; outvdd35 : linkage bit; outgnd34 : linkage bit; outvdd36 : linkage bit; outgnd35 : linkage bit; cgnd2 : linkage bit; cvdd2 : linkage bit; procmode : in bit; prst_neg : out bit; pint_neg : out bit; pfail_neg : in bit; outgnd36 : linkage bit; outvdd37 : linkage bit; pdaen_neg : inout bit; pcs_neg : inout bit; pas_neg : inout bit; pblast_neg : inout bit; pwait_neg : in bit; prdy_neg : out bit; pwnr : inout bit; outgnd37 : linkage bit; cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-21 outvdd38 : linkage bit; pbe3_neg : in bit; pbe2_neg : in bit; pbe1_neg : in bit; outgnd38 : linkage bit; outvdd39 : linkage bit; pbe0_neg : in bit; pbsel1 : in bit; pbsel0 : in bit; paddr1 : in bit; paddr0 : in bit; outgnd39 : linkage bit; outvdd40 : linkage bit; laddr18 : inout bit; laddr17 : inout bit; laddr16 : inout bit; laddr15 : inout bit; laddr14 : inout bit; outgnd40 : linkage bit; outvdd41 : linkage bit; laddr13 : inout bit; laddr12 : inout bit; laddr11 : inout bit; laddr10 : inout bit; laddr9 : inout bit; laddr8 : inout bit; outgnd41 : linkage bit; outvdd42 : linkage bit; laddr7 : inout bit; laddr6 : inout bit; laddr5 : inout bit; laddr4 : inout bit; laddr3 : inout bit; laddr2 : inout bit; outgnd42 : linkage bit; outvdd43 : linkage bit; laddr1 : out bit; laddr0 : out bit; outgnd43 : linkage bit; outvdd44 : linkage bit; outgnd44 : linkage bit; pvgg0 : linkage bit; cgnd3 : linkage bit; cvdd3 : linkage bit; stat1 : out bit ); appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-22 mindspeed technologies ? 28236-DSH-001-B -- libraries -- bcad won ? t recognize the reference to the work library. -- use work.std_1149_1_1994.all; use std_1149_1_1994.all; attribute component_conformance of cn8236 : entity is "std_1149_1_1993"; attribute pin_map of cn8236 : entity is physical_pin_map; constant bga_352: pin_map_string := "hfifowr0 : c2," & "hfifowr1 : d3," & "hfifowr2 : d2," & "hfifowr3 : d1," & "hfifowr4 : e3," & "hfifowr5 : f4," & "hswitch_neg: f3," & "stat0 : f1," & "rammode : g4," & "mwe3_neg : g3," & "mwe2_neg : g2," & "outgnd0 : g1," & "outvdd0 : h4," & "mwe1_neg : h3," & "mwe0_neg : h2," & "moe_neg : h1," & "mwr_neg : j4," & "outvdd1 : j3," & "mcs3_neg : j2," & "mcs2_neg : j1," & "mcs1_neg : k4," & "mcs0_neg : k3," & "outgnd1 : k2," & "outvdd2 : k1," & "hled_neg : l4," & "outvdd3 : l3," & "clkd3 : l2," & "outvdd4 : l1," & "outgnd2 : m3," & "sysclk : m2," & "outgnd3 : m1," & "clk2x : n4," & "outvdd5 : n3," & "outgnd4 : n2," & "ldata31 : n1," & "ldata30 : p1," & "ldata29 : p2," & cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-23 "ldata28 : p3," & "outvdd6 : p4," & "ldata27 : r1," & "ldata26 : r2," & "ldata25 : r3," & "ldata24 : r4," & "outgnd5 : t1," & "outvdd7 : t2," & "ldata23 : t3," & "ldata22 : t4," & "ldata21 : u1," & "outvdd8 : u2," & "ldata20 : u3," & "ldata19 : u4," & "ldata18 : v1," & "outgnd6 : v2," & "ldata17 : v3," & "ldata16 : v4," & "ldata15 : w1," & "ldata14 : w2," & "ldata13 : w3," & "outgnd7 : w4," & "ldata12 : y1," & "ldata11 : y2," & "ldata10 : y3," & "ldata9 : y4," & "ldata8 : aa1," & "outgnd8 : aa2," & "ldata7 : aa3," & "ldata6 : aa4," & "ldata5 : ab1," & "ldata4 : ab2," & "outvdd9 : ab3," & "rxdata15 : ae5," & "rxdata14 : af5," & "rxdata13 : ac6," & "rxdata12 : ad6," & "rxdata11 : ae6," & "rxdata10 : af6," & "rxdata9 : ac7," & "rxdata8 : ad7," & "ldata3 : ab4," & "ldata2 : ac1," & "ldata1 : ac2," & "ldata0 : ac3," & "outgnd9 : ad1," & "outvdd10 : ad2," & "schref : ae1," & appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-24 mindspeed technologies ? 28236-DSH-001-B "cgnd0 : af1," & "cvdd0 : ae2," & "outgnd10 : ac4," & "rxaddr4 : af2," & "rxaddr3 : ae3," & "rxaddr2 : af3," & "rxaddr1 : ad4," & "rxaddr0 : ae4," & "outgnd11 : af4," & "outvdd11 : ac5," & "rxpar : ad5," & "rxdata7 : ae7," & "rxdata6 : af7," & "rxdata5 : ac8," & "rxdata4 : ad8," & "rxdata3 : ae8," & "rxdata2 : af8," & "rxdata1 : ac9," & "outgnd12 : ad9," & "outvdd12 : ae9," & "rxdata0 : af9," & "rxsoc : ac10," & "rxen_neg : ad10," & "outgnd13 : ae10," & "rxclav_neg : ae11," & "outvdd13 : ac12," & "txclk : ad12," & "frcfg0 : ae12," & "frcfg1 : af12," & "frctrl : ac13," & "outgnd14 : ad13," & "outvdd14 : ae13," & "outgnd15 : af14," & "outvdd15 : ae14," & "utopia1 : ad14," & "txen_neg : ac14," & "txsoc : af15," & "txclav_neg : af16," & "txpar : ae16," & "txdata7 : af19," & "txdata6 : ae19," & "outgnd16 : ad19," & "outvdd16 : ac19," & "txdata5 : af20," & "txdata4 : ae20," & "txdata3 : ad20," & "txdata2 : ac20," & "txdata1 : af21," & cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-25 "txdata0 : ae21," & "outvdd17 : ad21," & "txaddr4 : ac21," & "txaddr3 : af22," & "txaddr2 : ae22," & "txaddr1 : ad22," & "txaddr0 : ac22," & "outgnd17 : af23," & "outvdd18 : ae23," & "outvdd19 : af24," & "cgnd1 : af26," & "cvdd1 : ae25," & "tclk : ac23," & "outvdd20 : ae26," & "trst_neg : ad25," & "tms : ad26," & "tdo : ac24," & "tdi : ac25," & "outvdd21 : ac26," & "scl : ab23," & "sda : ab24," & "pci5v : ab26," & "outgnd18 : aa23," & "outvdd22 : aa24," & "hint_neg : aa25," & "outvdd23 : ad16," & "txdata15 : ac16," & "txdata14 : af17," & "txdata13 : ae17," & "txdata12 : ad17," & "txdata11 : ac17," & "outgnd19 : af18," & "txdata10 : ae18," & "txdata9 : ad18," & "txdata8 : ac18," & "outvdd24 : aa26," & "hrst_neg : y23," & "outgnd20 : y24," & "hgnt_neg : y25," & "hreq_neg : y26," & "outgnd21 : w23," & "had31 : w24," & "had30 : w25," & "had29 : w26," & "outvdd25 : v23," & "had28 : v24," & "had27 : v25," & "had26 : v26," & appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-26 mindspeed technologies ? 28236-DSH-001-B "had25 : u23," & "had24 : u24," & "outgnd22 : u25," & "outvdd26 : u26," & "hcbe3_neg : t23," & "hidsel : t24," & "had23 : t25," & "outvdd27 : t26," & "had22 : r23," & "had21 : r24," & "had20 : r25," & "had19 : r26," & "outgnd23 : p23," & "had18 : p24," & "had17 : p25," & "had16 : p26," & "hcbe2_neg : n26," & "outgnd24 : n25," & "outvdd28 : n24," & "hclk : n23," & "outgnd25 : m26," & "hframe_neg : m25," & "hirdy_neg : m24," & "htrdy_neg : m23," & "hdevsel_neg: l26," & "hstop_neg : l25," & "hperr_neg : l24," & "hserr_neg : l23," & "outgnd26 : k26," & "outvdd29 : k25," & "hpar : k24," & "hcbe1_neg : k23," & "had15 : j26," & "had14 : j25," & "had13 : j24," & "outvdd30 : j23," & "outgnd27 : h26," & "had12 : h25," & "had11 : h24," & "had10 : h23," & "had9 : g26," & "had8 : g25," & "outgnd28 : g24," & "outvdd31 : g23," & "hcbe0_neg : f26," & "had7 : f25," & "had6 : f24," & "hfiford0 : c25," & cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-27 "hfiford1 : b26," & "hfiford2 : c24," & "hfiford3 : d23," & "hfiford4 : a25," & "hfiford5 : c23," & "henum_neg : b23," & "eepwr : d22," & "had5 : f23," & "had4 : e26," & "outgnd29 : e25," & "outvdd32 : e24," & "had3 : e23," & "had2 : d26," & "had1 : d25," & "had0 : d24," & "outgnd30 : c26," & "outgnd31 : a26," & "outvdd33 : b25," & "outgnd32 : b24," & "outvdd34 : a24," & "outgnd33 : a23," & "outvdd35 : d21," & "outgnd34 : c20," & "outvdd36 : b19," & "outgnd35 : a18," & "cgnd2 : d16," & "cvdd2 : c16," & "procmode : b16," & "prst_neg : a16," & "pint_neg : d15," & "pfail_neg : c15," & "outgnd36 : b14," & "outvdd37 : a14," & "pdaen_neg : b15," & "pcs_neg : a15," & "pas_neg : d14," & "pblast_neg : c14," & "pwait_neg : a13," & "prdy_neg : b13," & "pwnr : c13," & "outgnd37 : d13," & "outvdd38 : a12," & "pbe3_neg : b12," & "pbe2_neg : c12," & "pbe1_neg : d12," & "outgnd38 : a11," & "outvdd39 : b11," & "pbe0_neg : c11," & appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-28 mindspeed technologies ? 28236-DSH-001-B -- tap port name attributes attribute tap_scan_in of tdi : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_mode of tms : signal is true; attribute tap_scan_clock of tclk : signal is (1.0e+07, both); attribute tap_scan_reset of trst_neg : signal is true; -- instruction register attributes attribute instruction_length of cn8236 : entity is 4; "pbsel1 : d11," & "pbsel0 : a10," & "paddr1 : b10," & "paddr0 : c10," & "outgnd39 : d10," & "outvdd40 : a9," & "laddr18 : b9," & "laddr17 : c9," & "laddr16 : d9," & "laddr15 : a8," & "laddr14 : b8," & "outgnd40 : c8," & "outvdd41 : d8," & "laddr13 : a7," & "laddr12 : b7," & "laddr11 : c7," & "laddr10 : d7," & "laddr9 : a6," & "laddr8 : b6," & "outgnd41 : c6," & "outvdd42 : d6," & "laddr7 : a5," & "laddr6 : b5," & "laddr5 : c5," & "laddr4 : d5," & "laddr3 : a4," & "laddr2 : b4," & "outgnd42 : b3," & "outvdd43 : a2," & "laddr1 : c4," & "laddr0 : a3," & "outgnd43 : a1," & "outvdd44 : b2," & "outgnd44 : c1," & "pvgg0 : e4," & "cgnd3 : e2," & "cvdd3 : e1," & "stat1 : f2"; cn8236 appendix a: boundary scan atm servicesar plus with xbr traffic management a.6 boundary scan description language (bsdl) file 28236-DSH-001-B mindspeed technologies ? a-29 attribute instruction_opcode of cn8236 : entity is attribute instruction_capture of cn8236 : entity is "0001"; attribute instruction_private of cn8236 : entity is "rsthigh," & "tmwafifo," & "tmwbfifo," & "tmrfifo," & "tsegfifo," & "trsmfifo," & "t38afifo," & "t38bfifo," & "rsvd0," & "rsvd1," & "rsvd2"; end cn8236; "extest (0000)," & "rsthigh (0001)," & "sample (0010)," & "tmwafifo (0011)," & "tmwbfifo (0100)," & "tmrfifo (0101)," & "tsegfifo (0110)," & "trsmfifo (0111)," & "t38afifo (1000)," & "t38bfifo (1001)," & "idcode (1010)," & "highz (1011)," & "rsvd0 (1100)," & "rsvd1 (1101)," & "rsvd2 (1110)," & "bypass (1111)"; appendix a: boundary scan cn8236 a.6 boundary scan description language (bsdl) file atm servicesar plus with xbr traffic management a-30 mindspeed technologies ? 28236-DSH-001-B 28236-DSH-001-B mindspeed technologies ? b-31 b appendix b: list of acronyms a aal atm adaption layer abr available bit rate acr allowed cell rate atm asynchronous transfer mode b basize buffer allocation size bga ball grid array bom beginning of message bsdl boundary scan description language btag beginning tag c cbr constant bit rate ccr current cell rate cdv cell delay variation cdvt cell delay variation tolerance clp cell loss priority clr cell loss ratio ci congestion indication com continuation of message cpcs common part convergence sublayer cpi common part indicator cpu central processing unit crc cyclic redundancy check csr control and status registers ctd cell transfer delay d de discard eligibility dma direct memory access e edc error detection code eom end of message epd early packet discard er explicit rate etag ending tag evs evaluation system appendix b: list of acronyms cn8236 atm servicesar plus with xbr traffic management b-32 mindspeed technologies ? 28236-DSH-001-B f fifo first in first out g gcra generic cell rate algorithm gfc generic flow control gfr guaranteed frame rate gpio general purpose input/output i ietf internet engineering task force ilmi interim local management interface j jtag joint test action group l lane lan emulation lec lan emulation client lecid lan emulation client id len length lsb least significant bit m mbit megabit mbps megabits per second mbs maximum burst size mib management information base msb most significant bit n ni no increase nic network interface card nni network-to-network interface o oam operation and maintenance p pci peripheral component interconnect pcr peak cell rate pdu protocol data unit pfe package forward engine phy physical layer device pm performance monitoring pti payload type identifier pvc permanent virtual connections (circuit) q qos quality of service cn8236 appendix b: list of acronyms atm servicesar plus with xbr traffic management 28236-DSH-001-B mindspeed technologies ? b-33 r rdb rate decision block rdf rate decrease factor rm resource management rr relative rate rsm reassembly coprocessor s sam service access multiplexer sbd segmentation buffer descriptor scr sustainable cell rate sdu service data unit seg segmentation coprocessor servicesar service segmentation and reassembly controller smds switched multimegabit data service snmp simple network management protocol sram static random access memory src segmentation and reassembly controller chip ssm single segment message st segment type svc switched virtual circuit (connection) u uni user-to-network interface utopia universal test and operation physical interface for atm uu user-to-user t tcr tagged cell rate ttl transistor-transistor logic u ubr unspecified bit rate v vbr variable bit rate vc virtual circuit vcc virtual channel connection vci virtual channel identifier vp virtual path vpi virtual path identifier appendix b: list of acronyms cn8236 atm servicesar plus with xbr traffic management b-34 mindspeed technologies ? 28236-DSH-001-B w w w . m i n d s p e e d . c o m general information: u.s. and canada: (800) 854-8099 international: (949) 483-6996 headquarters - newport beach 4311 jamboree rd. p.o. box c newport beach, ca. 92658-8902 |
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